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PDF HM5425401BTT-10 Data sheet ( Hoja de datos )
| Número de pieza | HM5425401BTT-10 | |
| Descripción | 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 16-bit 4-bank/8-Mword 8-bit 4-bank/ 16-Mword 4-bit 4-bank | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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HM5425161B Series
HM5425801B Series
HM5425401B Series
256M SSTL_2 interface DDR SDRAM
143 MHz/133 MHz/125 MHz/100 MHz
4-Mword × 16-bit × 4-bank/8-Mword × 8-bit × 4-bank/
16-Mword × 4-bit × 4-bank
E0086H20 (Ver. 2.0)
Jan. 23, 2002
Description
The HM5425161B, the HM5425801B and the HM5425401B are the Double Data Rate (DDR) SDRAM
devices. Read and write operations are performed at the cross points of the CLK and the CLK. This high
speed data transfer is realized by the 2-bit prefetch piplined architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus design. By setting extended mode resistor, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
Features
• 2.5 V power supply
• SSTL-2 interface for all inputs and outputs
• Clock frequency: 143 MHz/133 MHz/125 MHz/100 MHz (max)
• Data inputs, outputs, and DM are synchronized with DQS
• 4 banks can operate simultaneously and independently
• Burst read/write operation
• Programmable burst length: 2/4/8
Burst read stop capability
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
1 page  
HM5425161B, HM5425801B, HM5425401B Series
Pin Arrangement (HM5425801B)
66-pin TSOP
VCC
DQ0
VCCQ
NC
DQ1
VSSQ
NC
DQ2
VCCQ
NC
DQ3
VSSQ
NC
NC
VCCQ
NC
NC
VCC
NC
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66 VSS
65 DQ7
64 VSSQ
63 NC
62 DQ6
61 VCCQ
60 NC
59 DQ5
58 VSSQ
57 NC
56 DQ4
55 VCCQ
54 NC
53 NC
52 VSSQ
51 DQS
50 NC
49 VREF
48 VSS
47 DM
46 CLK
45 CLK
44 CKE
43 NC
42 A12
41 A11
40 A9
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
(Top view)
Data Sheet E0086H20
5
5 Page 
HM5425161B, HM5425801B, HM5425401B Series
Pin Functions (2)
DM, DMU/DML (input pins): DM (the HM5425801B and the HM5425401B), DMU/DML (the
HM5425161B) are the reference signals of the data input mask function. DMs are sampled at the cross point
of DQS and VREF. DMU/DML provide the byte mask function. When DMU/DML = High, the data input at
the same timing are masked while the internal burst counter will be count up. DML controls the lower byte
(DQ0 to DQ7) and DMU controls the upper byte (DQ8 to DQ15) of write data.
DQ0 to DQ15 (input and output pins): Data are input to and output from these pins (the DQ0 to the DQ15;
the HM5425161B, the DQ0 to the DQ7; the HM5425801B, the DQ0 to the DQ3; the HM5425401B).
DQS, DQSU/DQSL (input and output pin): DQS (the HM5425801B and the HM5425401B),
DQSU/DQSL (the HM5425161B) provide the read data strobes (as output) and the write data strobes (as
input). DQSL is the lower byte (DQ0 to DQ7) data strobe signal, DQSU is the upper byte (DQ8 to DQ15)
data strobe signal.
VCC and VCCQ (power supply pins): 2.5 V is applied. (VCC is for the internal circuit and VCCQ is for the
output buffer.)
VSS and VSSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the
output buffer.)
Data Sheet E0086H20
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HM5425401BTT-10.PDF ] | |
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