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HM62G18512 PDF даташит

Спецификация HM62G18512 изготовлена ​​​​«Hitachi Semiconductor» и имеет функцию, называемую «8M Synchronous Fast Static RAM(512k-word x 18-bit)».

Детали детали

Номер произв HM62G18512
Описание 8M Synchronous Fast Static RAM(512k-word x 18-bit)
Производители Hitachi Semiconductor
логотип Hitachi Semiconductor логотип 

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HM62G18512 Даташит, Описание, Даташиты
HM62G18512 Series
8M Synchronous Fast Static RAM
(512k-word × 18-bit)
ADE-203-1185 (Z)
Preliminary
Rev. 0.0
Jun. 12, 2000
Description
The HM62G18512 is a synchronous fast static RAM organized as 512-kword × 18-bit. It has realized high
speed access time by employing the most advanced CMOS process and high speed circuit designing
technology. It is most appropriate for the application which requires high speed, high density memory and
wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119-
bump BGA.
Note: All power supply and ground pins must be connected for proper operation of the device.
Features
Power supply: 3.3 V +10%, –5%
Clock frequency: 200 MHz to 250 MHz
Internal self-timed late write
Byte write control (2 byte write selects, one for each 9-bit)
Optional ×36 configuration
HSTL compatible I/O
Programmable impedance output drivers
User selective input trip-point
Differential, HSTL clock inputs
Asynchronous G output control
Asynchronous sleep mode
Limited set of boundary scan JTAG IEEE 1149.1 compatible
Protocol: Single clock register-register mode
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specifications.









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HM62G18512 Даташит, Описание, Даташиты
HM62G18512 Series
Ordering Information
Type No.
HM62G18512BP-4
HM62G18512BP-5
Access time
2.1 ns
2.5 ns
Cycle time
4.0 ns
5.0 ns
Package
119-bump 1. 27 mm
14 mm × 22 mm BGA (BP-119A)
Pin Arrangement
119-bumps BGA
1234567
A
VDDQ SA0 SA6 NC SA4 SA2 VDDQ
B
NC NC SA7 NC SA8 SA18 NC
C
NC SA13 SA3 VDD SA5 SA1 NC
D
DQb0 NC VSS ZQ VSS DQa4 NC
E
NC DQb1 VSS SS VSS NC DQa5
F
VDDQ NC VSS G VSS DQa6 VDDQ
G
NC DQb2 SWEb NC VSS NC DQa7
H
DQb3 NC VSS NC VSS DQa8 NC
J
VDDQ VDD VREF VDD VREF VDD VDDQ
K
NC DQb8 VSS K VSS NC DQa3
L
DQb7 NC VSS K SWEa DQa2 NC
M
VDDQ DQb6 VSS SWE VSS NC VDDQ
N
DQb5 NC VSS SA16 VSS DQa1 NC
P
NC DQb4 VSS SA14 VSS NC DQa0
R
NC SA9 M1 VDD M2 SA10 NC
T
NC SA17 SA11 NC SA12 SA15 ZZ
U
VDDQ TMS TDI TCK TDO NC VDDQ
(Top view)
2









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HM62G18512 Даташит, Описание, Даташиты
Pin Description
Name
VDD
VSS
VDDQ
VREF
K
K
SS
SWE
SAn
SWEx
G
ZZ
ZQ
DQxn
I/O type
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
M1, M2
TMS
TCK
TDI
TDO
NC
Input
Input
Input
Input
Output
HM62G18512 Series
Descriptions
Core power supply
Ground
Output power supply
Input reference: provides input reference voltage
Clock input. Active high.
Clock input. Active low.
Synchronous chip select
Synchronous write enable
Synchronous address input
Synchronous byte write enables
Asynchronous output enable
Power down mode select
Output impedance control
Synchronous data input/output
Output protocol mode select
Boundary scan test mode select
Boundary scan test clock
Boundary scan test data input
Boundary scan test data output
No connection
Notes
n = 0, 1, 2...18
x = a, b
1
x = a, b
n = 0, 1, 2...8
M1 M2 Protocol
Notes
VSS
VDD
Synchronous register to register operation
2
Notes: 1. ZQ is to be connected to VSS via a resistance RQ where 150 Ω ≤ RQ 300 , if ZQ = VDDQ or
open, output buffer impedance will be maximum. A case of minimum impedance, it needs to
connect over 120 between ZQ and VSS.
2. There is 1 protocol with mode pin. Mode control pins (M1, M2) are to be tied either VDD or VSS
respectively. The state of the Mode control inputs must be set before power-up and must not
change during device operation. Mode control inputs are not standard inputs and may not meet
VIH or VIL specification. This SRAM is tested only in the synchronous register to register
operation.
3










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