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PDF HM62W8512BLTTI-7 Data sheet ( Hoja de datos )
| Número de pieza | HM62W8512BLTTI-7 | |
| Descripción | 4 M SRAM (512-kword x 8-bit) | |
| Fabricantes | Hitachi Semiconductor | |
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HM62W8512BI Series
4 M SRAM (512-kword × 8-bit)
ADE-203-1086A (Z)
Rev. 1.0
Jul. 13, 1999
Description
The Hitachi HM62W8512BI is a 4-Mbit static RAM organized 512-kword × 8-bit. HM62W8512BI Series
has realized higher density, higher performance and low power consumption by employing Hi-CMOS process
technology. The HM62W8512BI Series offers low power standby power dissipation; therefore, it is suitable
for battery backup systems. It is packaged in standard 32-pin TSOP II.
Features
• Single 3.3 V supply: 3.3 V ± 0.3V
• Access time: 70/85 ns (max)
• Power dissipation
Active: 16.5 mW/MHz (typ)
Standby: 3.3 µW (typ)
• Completely static memory. No clock or timing strobe required
• Equal access and cycle times
• Common data input and output: Three state output
• Directly LV-TTL compatible: All inputs and outputs
• Battery backup operation
• Operating temperature: –40 to +85˚C
Ordering Information
Type No.
HM62W8512BLTTI-7
HM62W8512BLTTI-8
Access time
70 ns
85 ns
Package
400-mil 32-pin plastic TSOP II (TTP-32D)
1 page  
HM62W8512BI Series
DC Characteristics (Ta = –40 to +85°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
Parameter
Symbol Min
Typ*1 Max Unit Test conditions
Input leakage current
Output leakage current
|ILI|
|ILO|
Operating power
supply current: DC
I CC
Operating power supply current ICC1
—
—
—
—
Operating power
supply current
I CC2
—
Standby power supply
current: DC
ISB —
— 1 µA Vin = VSS to VCC
— 1 µA CS = VIH or OE = VIH or
WE = VIL, VI/O = VSS to VCC
— 10 mA CS = VIL,
others = VIH/VIL, II/O = 0 mA
— 45 mA Min cycle, duty = 100%
CS = VIL, others = VIH/VIL
II/O = 0 mA
5 10 mA Cycle time = 1 µs,
duty = 100%
II/O = 0 mA, CS ≤ 0.2 V
VIH ≥ VCC – 0.2 V,
VIL ≤ 0.2 V
0.1 0.3 mA CS = VIH
Standby power supply
current (1): DC
ISB1 —
1*2 40*2 µA Vin ≥ 0 V,
CS ≥ VCC – 0.2 V
Output low voltage
VOL —
— 0.4 V IOL = 2.0 mA
— — 0.2 V IOL = 100 µA
Output high voltage
VOH VCC – 0.2 — — V IOH = –100 µA
2.4 — — V IOH = –2.0 mA
Note: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and specified loading, and not guaranteed.
2. This characteristics is guaranteed only for L-version.
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter
Symbol
Typ
Max
Input capacitance*1
Cin
—
8
Input/output capacitance*1 CI/O
—
10
Note: 1. This parameter is sampled and not 100% tested.
Unit
pF
pF
Test conditions
Vin = 0 V
VI/O = 0 V
5
5 Page 
HM62W8512BI Series
Low VCC Data Retention Characteristics (Ta = –40 to +85°C)
Parameter
Symbol Min Typ Max Unit Test conditions*2
VCC for data retention
Data retention current
VDR
I CCDR
2 —— V
— 0.8*3 20*1 µA
CS ≥ VCC – 0.2 V, Vin ≥ 0 V
VCC = 3.0 V, Vin ≥ 0 V
CS ≥ VCC – 0.2 V
Chip deselect to data retention time tCDR
0 — — ns
See retention waveform
Operation recovery time
tR
tRC*4 —
—
ns
Notes: 1. For L-version and 10 µA (max.) at Ta = –40 to +40°C.
2. CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin
levels (address, WE, OE, I/O) can be in the high impedance state.
3. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
4. tRC = read cycle time.
Low VCC Data Retention Timing Waveform (CS Controlled)
VCC
3.0 V
tCDR
Data retention mode
tR
2.4 V
VDR
CS
0V
CS ≥ VCC – 0.2 V
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HM62W8512BLTTI-7.PDF ] | |
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