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PDF AMC0XXCFLKA Data sheet ( Hoja de datos )
| Número de pieza | AMC0XXCFLKA | |
| Descripción | 1/ 2/ 4/ or 10 Megabyte 5.0 V-only Flash Memory PC Card | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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FINAL
AmC0XXCFLKA
1, 2, 4, or 10 Megabyte 5.0 V-only Flash Memory PC Card
DISTINCTIVE CHARACTERISTICS
s High performance
— 150 ns maximum access time
s Single supply operation
— Write and erase voltage, 5.0 V ±5%
— Read voltage, 5.0 V ±5%
s CMOS low power consumption
— 45 mA maximum active read current (x8 mode)
— 65 mA maximum active erase/write current
(x8 mode)
s High write endurance
— Minimum 100,000 erase/write cycles
s PCMCIA/JEIDA 68-pin standard
— Selectable byte- or word-wide configuration
s Write protect switch
— Prevents accidental data loss
s Zero data retention power
— Batteries not required for data storage
s Separate attribute memory
— 512 byte EEPROM
s Automated write and erase operations increase
system write performance
— 64K byte memory sectors for faster automated
erase speed
— Typically 1.5 seconds per single memory sector
erase
— Random address writes to previously erased
bytes (16 µs typical per byte)
s Total system integration solution
— Support from independent software and
hardware vendors
s Low insertion and removal force
— State-of-the-art connector allows for minimum
card insertion and removal effort
s Sector erase suspend/resume
— Suspend the erase operation to allow a read
operation in another sector within the same
device
GENERAL DESCRIPTION
AMD’s 5.0 V-only Flash Memory PC Card provides the
highest system level performance for data and file stor-
age solutions to the portable PC market segment. Man-
ufactured with AMD’s Negative Gate Erase, 5.0 V-only
technology, the AMD 5.0 V-only Flash Memory Cards
are the most cost-effective and reliable approach to
single-supply Flash memory cards. Data files and ap-
plication programs can be stored on the “C” series
cards. This allows OEM manufacturers of portable sys-
tems to eliminate the weight, high power consumption
and reliability issues associated with electromechanical
disk-based systems. The “C” series cards also allow to-
day’s bulky and heavy battery packs to be reduced in
weight and size. Typically only two “AA” alkaline batter-
ies are required for total system operation. AMD’s
Flash Memory PC Cards provide the most efficient
method to transfer useful work between different hard-
ware platforms. The enabling technology of the “C” se-
ries cards enhances the productivity of mobile workers.
Widespread acceptance of the “C” series cards is as-
sured due to their compatibility with the 68-pin PCM-
CIA/JEIDA international standard. AMD’s Flash
Memory Cards can be read in either a byte-wide or
word-wide mode which allows for flexible integration
into various system platforms. Compatibility is assured
at the hardware interface and software interchange
specification. The Card Information Structure (CIS) or
Metaformat, can be written by the OEM at the memory
card’s attribute memory address space beginning at
address 00000H by using a format utility. The CIS ap-
pears at the beginning of the Card’s attribute memory
space and defines the low-level organization of data on
the PC Card. The “C” series cards contains a separate
512 byte EEPROM memory for the cards’ attribute
memory space. This allows all of the Flash memory to
be used for the common memory space.
Third party software solutions such as Microsoft’s
Flash File System (FFS), M-System’s True FFS, and
SCM’s SCM-FFS, enable AMD’s Flash Memory PC
Card to replicate the function of traditional disk-based
memory systems.
Publication# 18723 Rev: C Amendment/+1
Issue Date: May 1998
1 page  
PIN DESCRIPTION
A0–A23
Address Inputs
These inputs are internally latched during write cycles.
BVD1, BVD2
Battery Voltage Detect
Internally pulled-up.
CD1, CD2
Card Detect
When card detect 1 and 2 = ground the system detects
the card.
CE1, CE2
Card Enable
This input is active low. The memory card is deselected
and power consumption is reduced to standby levels
when CE is high. CE activates the internal memory
card circuitry that controls the high and low byte control
logic of the card, input buffers segment decoders, and
associated memory devices.
D0–D15
Data Input/Output
Data inputs are internally latched on write cycles. Data
outputs during read cycles. Data pins are active high.
When the memory card is deselected or the outputs
are disabled the outputs float to tristate.
GND
Ground
NC
No Connect
Corresponding pin is not connected internally to the die.
OE
Output Enable
This input is active low and enables the data buffers
through the card outputs during read cycles.
REG
Attribute Memory Select
This input is active low and enables reading the CIS
from the EEPROM.
VCC
PC Card Power Supply
For device operation (5.0 V ± 5%).
WE
Write Enable
This input is active low and controls the write function
of the command register to the memory array. The
target address is latched on the falling edge of the WE
pulse and the appropriate data is latched on the rising
edge of the pulse.
WP
Write Protect
This output is active high and disables all card write
operations.
MEMORY CARD OPERATIONS
The “C” series Flash Memory Card is organized as an
array of individual devices. Each device is 512K bytes
in size with eight 64K byte sectors. Although the ad-
dress space is continuous each physical device defines
a logical address segment size.
Byte-wide erase operations could be performed in
four ways:
s In increments of the segment size
s In increments of the sectors in individual segments
s All eight sectors in parallel within individual
segments
s Selected sectors of the eight sectors in parallel
within individual segments
Multiple segments may be erased concurrently when
additional ICC current is supplied to the device. Once a
memory sector or memory segment is erased any ad-
dress location may be programmed. Flash technology
allows any logical “1” data bit to be programmed to a
logical “0”. The only way to reset bits to a logical “1” is
to erase the entire memory sector of 64K bytes or
memory segment of 512K bytes.
Erase operations are the only operations that work on
entire memory sectors or memory segments. All other
operations such as word-wide programming are not af-
fected by the physical memory segments.
The common memory space data contents are altered
in a similar manner as writing to individual Flash mem-
ory devices. On-card address and data buffers activate
the appropriate Flash device in the memory array. Each
device internally latches address and data during write
cycles. Refer to Table 1.
Attribute memory is a separately accessed card mem-
ory space. The register memory space is active when
the REG pin is driven low. The Card Information Struc-
ture (CIS) describes the capabilities and specification
of a card. The CIS is stored in the attribute memory
space beginning at address 00000H. The “C” series
cards contain a separate 512 byte EEPROM memory
for the Card Information Structure. D0–D7 are active
during attribute memory accesses. D8–D15 should be
ignored. Odd order bytes present invalid data. Refer to
Table 2.
5/4/98
AmC0XXCFLKA
5
5 Page 
Table 5. Word Command Definitions (Note 7)
Embedded
Command
Sequence
Bus
Write
Cycles
Req’d
First Bus
Write Cycle
Addr* Data
Second Bus
Write Cycle
Addr* Data
Third Bus
Write Cycle
Addr* Data
Fourth Bus
Read/Write Cycle
Addr* Data
Fifth Bus
Write Cycle
Addr* Data
Sixth Bus
Write Cycle
Addr* Data
Reset/Read
4 AAAAH AAAA 5554H 5555 AAAAH F0F0 RA
RW
Autoselect
4
AAAAH AAAA 5554H 5555 AAAAH 9090 00H/02H
0101/
A4A4
Byte Write
4 AAAAH AAAA 5554H 5555 AAAAH A0A0 PA
PW
Segment Erase 6 AAAAH AAAA 5554H 5555 AAAAH 8080 AAAAH AAAA 5554H 5555 AAAAH 1010
Sector Erase
6 AAAAH AAAA 5554H 5555 AAAAH 8080 AAAAH AAAA 5554H 5555 SA 3030
Sector Erase Suspend Erase can be suspended during sector erase with Addr (don’t care), Data (B0H)
Sector Erase Resume Erase can be resumed after suspend with Addr (don’t care), Data (30H)
Notes:
1. Address bit A16 = X = Don’t Care for all address commands except for Program Address (PA) and Sector Address (SA).
2. Bus operations are defined in Table 1.
3. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A17, A18, A19 will uniquely select any sector of a segment.
To select the memory segment:1 and 2 Mbyte: Use CE1, CE2, A20
4 Mbyte:
Use CE1, CE2, A20, A21
0 Mbyte:
Use CE1, CE2, A20–A23.
4. RW = Data read from location RA during read operation. (Word Mode).
PW = Data to be programmed at location PA. Data is latched on the rising edge of WE. (Word Mode).
5. Address for Memory Segment Pair 0 (S0 and S1) only. Address for the higher Memory Segment Pairs (S2, S3 = Pair 1, S4,
S5 = Pair 2, S6, S7 = Pair 3…) is equal to (Addr) + M* (80000H) where M = Memory Segment Pair number.
6. Word = 2 bytes = odd byte and even byte.
7. CE1 = 0 and CE2 = 0.
Table 6. Memory Sector Address Table
for Memory Segment S0
Sector A19 A18 A17 Address Range
0 0 0 0 00000h-0FFFFh
1 0 0 1 10000h-1FFFFh
2 0 1 0 20000h-2FFFFh
3 0 1 1 30000h-3FFFFh
4 1 0 0 40000h-4FFFFh
5 1 0 1 50000h-5FFFFh
6 1 1 0 60000h-6FFFFh
7 1 1 1 70000h-7FFFFh
Note: A0 is not mapped internally.
FLASH MEMORY WRITE/ERASE
OPERATIONS
Details of AMD’s Embedded Write and
Erase Operations
Embedded Erase™ Algorithm
The automatic memory sector or memory segment
erase does not require the device to be entirely prepro-
gramming prior to executing the Embedded Erase
command. Upon executing the Embedded Erase com-
mand sequence, the addressed memory sector or
memory segment will automatically write and verify the
entire memory segment or memory sector for an all
“zero” data pattern. The system is not required to pro-
vide any controls or timing during these operations.
When the memory sector or memory segment is auto-
matically verified to contain an all “zero” pattern, a
self-timed chip erase-and-verify begins. The erase and
verify operations are complete when the data on D7 of
the memory sector or memory segment is “1” (see
“Write Operation Status” section) at which time the
5/4/98
AmC0XXCFLKA
11
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