M27W800-120B6TR Datasheet PDF - STMicroelectronics
| Part Number | M27W800-120B6TR | |
| Description | 8 Mbit 1Mb x 8 or 512Kb x 16 Low Voltage UV EPROM and OTP EPROM | |
| Manufacturers | STMicroelectronics | |
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M27W800
8 Mbit (1Mb x 8 or 512Kb x 16)
Low Voltage UV EPROM and OTP EPROM
s 2.7V to 3.6V LOW VOLTAGE in READ
OPERATION
s ACCESS TIME:
– 90ns at VCC = 3.0V to 3.6V
– 100ns at VCC = 2.7V to 3.6V
s BYTE-WIDE or WORD-WIDE
CONFIGURABLE
s 8 Mbit MASK ROM REPLACEMENT
s LOW POWER CONSUMPTION
– Active Current 30mA at 8MHz
– Standby Current 15µA
s PROGRAMMING VOLTAGE: 12.5V ± 0.25V
s PROGRAMMING TIME: 50µs/word
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: B2h
DESCRIPTION
The M27W800 is a low voltage 8 Mbit EPROM of-
fered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large data or
program storage. It is organised as either 1 Mbit
words of 8 bit or 512 Kbit words of 16 bit. The pin-
out is compatible with a 8 Mbit Mask ROM.
The M27W800 operates in the read mode with a
supply voltage as low as 2.7V. The decrease in
operating power allows either a reduction of the
size of the battery or an increase in the time be-
tween battery recharges.
The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written rapidly to
the device by following the programming proce-
dure.
For applications where the content is programmed
only one time and erasure is not required, the
M27W800 is offered in PDIP42 and PLCC44 pack-
age.
42
1
FDIP42W (F)
42
1
PDIP42 (B)
PLCC44 (K)
Figure 1. Logic Diagram
VCC
19
A0-A18
E
G
BYTEVPP
M27W800
Q15A–1
15
Q0-Q14
VSS
AI03601
March 2000
1/15
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M27W800
Table 7. Read Mode DC Characteristics (1)
(TA = –40 to 85 °C; VCC = 2.7 to 3.6V; VPP = VCC)
Symbol
Parameter
Test Condition
Min
ILI Input Leakage Current
ILO Output Leakage Current
ICC Supply Current
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
E = VIL, G = VIL, IOUT = 0mA,
f = 8MHz, VCC ≤ 3.6V
E = VIL, G = VIL, IOUT = 0mA,
f = 5MHz, VCC ≤ 3.6V
ICC1 Supply Current (Standby) TTL
E = VIH
ICC2 Supply Current (Standby) CMOS
IPP Program Current
VIL Input Low Voltage
E > VCC – 0.2V, VCC ≤ 3.6V
VPP = VCC
–0.6
VIH (2) Input High Voltage
0.7VCC
VOL Output Low Voltage
IOL = 2.1mA
VOH Output High Voltage TTL
IOH = –400µA
2.4
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Maximum DC voltage on Output is VCC +0.5V.
Max
±1
±10
30
20
1
15
10
0.2VCC
VCC + 0.5
0.4
Unit
µA
µA
mA
mA
mA
µA
µA
V
V
V
V
Standby Mode
The M27W800 has a standby mode which reduc-
es the supply current from 20mA to 20µA with low
voltage operation VCC ≤ 3.6V, see Read Mode DC
Characteristics table for details.The M27W800 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current ICC
has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E. The magnitude of the
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device out-
puts. The associated transient voltage peaks can
be suppressed by complying with the two line out-
put control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor is used on every device between VCC
and VSS. This should be a high frequency type of
low inherent inductance and should be placed as
close as possible to the device. In addition, a
4.7µF electrolytic capacitor should be used be-
tween VCC and VSS for every eight devices. This
capacitor should be mounted near the power sup-
ply connection point. The purpose of this capacitor
is to overcome the voltage drop caused by the in-
ductive effects of PCB traces.
5/15
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