M27C202-80K3TR Datasheet PDF - STMicroelectronics
| Part Number | M27C202-80K3TR | |
| Description | 2 Mbit 128Kb x16 UV EPROM and OTP EPROM | |
| Manufacturers | STMicroelectronics | |
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M27C202
2 Mbit (128Kb x16) UV EPROM and OTP EPROM
s 5V ± 10% SUPPLY VOLTAGE in READ
OPERATION
s ACCESS TIME: 45ns
s LOW POWER CONSUMPTION:
– Active Current 50mA at 5MHz
– Standby Current 100µA
s PROGRAMMING VOLTAGE: 12.75V ± 0.25V
s PROGRAMMING TIME: 100µs/word
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 1Ch
DESCRIPTION
The M27C202 is a 2 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for micro-
processor systems requiring large programs, in
the application where the contents is stable and
needs to be programmed only one time, and is or-
ganised as 131,072 by 16 bits.
The FDIP40W (window ceramic frit-seal package)
has a transparent lids which allow the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C202 is offered in PDIP40, PLCC44 and
TSOP40 (10 x 14 mm) packages.
40
1
FDIP40W (F)
40
1
PDIP40 (B)
PLCC44 (K)
TSOP40 (N)
10 x 14 mm
Figure 1. Logic Diagram
VCC VPP
17
A0-A16
16
Q0-Q15
P M27C202
E
G
VSS
AI01815
April 1999
1/15
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M27C202
Table 7. Read Mode DC Characteristics (1)
(TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C; VCC = 5V ± 10%; VPP = VCC)
Symbol
Parameter
Test Condition
Min
ILI Input Leakage Current
ILO Output Leakage Current
ICC Supply Current
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
E = VIL, G = VIL,
IOUT = 0mA, f = 5MHz
ICC1 Supply Current (Standby) TTL
ICC2 Supply Current (Standby) CMOS
IPP Program Current
VIL Input Low Voltage
E = VIH
E > VCC – 0.2V
VPP = VCC
–0.3
VIH (2) Input High Voltage
2
VOL Output Low Voltage
IOL = 2.1mA
Output High Voltage TTL
VOH
Output High Voltage CMOS
IOH = –400µA
IOH = –100µA
2.4
VCC – 0.7V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Maximum DC voltage on Output is VCC +0.5V.
Max
±10
±10
50
1
100
100
0.8
VCC + 1
0.4
Unit
µA
µA
mA
mA
µA
µA
V
V
V
V
V
Two Line Output Control
Because OTP EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device at the
output. The associated transient voltage peaks
can be suppressed by complying with the two line
output control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
ic capacitor be used on every device between VCC
and VSS. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between VCC and VSS for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/15
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