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HY57V651620BTC-6 PDF даташит

Спецификация HY57V651620BTC-6 изготовлена ​​​​«Hynix Semiconductor» и имеет функцию, называемую «4 Banks x 1M x 16Bit Synchronous DRAM».

Детали детали

Номер произв HY57V651620BTC-6
Описание 4 Banks x 1M x 16Bit Synchronous DRAM
Производители Hynix Semiconductor
логотип Hynix Semiconductor логотип 

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HY57V651620BTC-6 Даташит, Описание, Даташиты
HY57V651620B
4 Banks x 1M x 16Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.
H Y 5 7 V 6 4 1 6 2 0 H G i s o f f e r i n g f u l l y s y n c h r o n o u s o p e r a t i o n r e f e r e n c e d t o a p o s i t i v e e d g e o f t h e c l o c k . A l l i n p u t s a n d o u t p u t s a r e s y nc h r o -
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
P r o g r a m m a b l e o p t i o n s i n c l u d e t h e l e n g t h o f p i p e l i n e ( R e a d l a t e n c y o f 2 o r 3 ) , t h e n u m b e r o f c o n s e c u t i v e r e a d o r w r i t e c y c l e s i n it i a t e d
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
r e a d o r w r i t e c y c l e s i n p r o g r e s s c a n b e t e r m i n a t e d b y a b u r s t t e r m i n a t e c o m m a n d o r c a n b e i n t e r r u p t e d a n d r e p l a c e d b y a n e w b u r st
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply Note)
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by UDQM or LDQM
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
• Internal four banks operation
ORDERING INFORMATION
Part No.
HY57V651620BTC-55
HY57V651620BTC-6
HY57V651620BTC-7
HY57V651620BTC-75
HY57V651620BTC-8
HY57V651620BTC-10P
HY57V651620BTC-10S
HY57V651620BTC-10
HY57V651620BLTC-55
HY57V651620BLTC-6
HY57V651620BLTC-7
HY57V651620BLTC-75
HY57V651620BLTC-8
HY57V651620BLTC-10P
HY57V651620BLTC-10S
HY57V651620BLTC-10
Clock Frequency
183MHz
166MHz
143MHz
133MHz
125MHz
100MHz
100MHz
100MHz
183MHz
166MHz
143MHz
133MHz
125MHz
100MHz
100MHz
100MHz
Power
Organization Interface
Normal
4Banks x 1Mbits
x16
LVTTL
Low power
Package
400mil 54pin TSOP II
Note : VDD(Min) of HY57V651620B(L)TC-55/6/7 is 3.135V
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 1.9/Apr.01









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HY57V651620BTC-6 Даташит, Описание, Даташиты
PIN CONFIGURATION
PIN DESCRIPTION
VDD
DQ0
V DDQ
DQ1
DQ2
V SSQ
DQ3
DQ4
V DDQ
DQ5
DQ6
V SSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
5 4 V SS
53 DQ15
5 2 V SSQ
51 DQ14
50 DQ13
4 9 V DDQ
48 DQ12
47 DQ11
4 6 V SSQ
45 DQ10
44 DQ9
4 3 V DDQ
42 DQ8
4 1 V SS
40 NC
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
2 8 V SS
HY57V651620B
PIN
CLK
CKE
CS
BA0,BA1
A0 ~ A11
R A S , C A S, W E
LDQM, UDQM
DQ0 ~ DQ15
V DD /V SS
V D D Q /V S S Q
NC
PIN NAME
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during R A S activity
Selects bank to be read/written during C A S activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and W E define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Rev. 1.9/Apr.01
2









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HY57V651620BTC-6 Даташит, Описание, Даташиты
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Synchronous DRAM
HY57V651620B
Self refresh logic
& timer
Internal Row
counter
CLK
CKE
CS
RAS
CAS
WE
UDQM
LDQM
Row active
Row
Pre
Decoders
refresh
Column
Active
Column
Pre
Decoders
1Mx16 Bank 3
1Mx16 Bank 2
1Mx16 Bank 1
1Mx16 Bank 0
Memory
Cell
Array
Y decoders
DQ0
DQ1
DQ14
DQ15
Bank Select
Column Add
Counter
A0 Address
A1 Registers
Burst
Counter
A11
BA0
BA1
Mode Registers
CAS Latency
Data Out Control Pipe Line Control
Rev. 1.9/Apr.01
3










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