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PDF HY628100AG Data sheet ( Hoja de datos )
| Número de pieza | HY628100AG | |
| Descripción | 128Kx8bit CMOS SRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY628100A Series
128Kx8bit CMOS SRAM
DESCRIPTION
FEATURES
The HY628100A is a high speed, low power and
1M bit CMOS Static Random Access Memory
organized as 131,072 words by 8bit. The
HY628100A uses high performance CMOS
process technology and designed for high speed
low power circuit technology. It is particulary well
suited for used in high density low power system
application. This device has a data retention
mode that guarantees data to remain valid at a
minimum power supply voltage of 2.0V.
• Fully static operation and Tri-state output
• TTL compatible inputs and outputs
• Battery backup(L/LL-part)
- 2.0V(min) data retention
• Standard pin configuration
- 32pin 525mil SOP
- 32pin 8x20mm TSOP-I(Standard)
Product
Voltage Speed Operation
No (V) (ns) Current(mA)
HY628100A
5.0 55/70/85
10
Comment : 50ns is available with 30pF test load.
Standby Current(uA)
L LL
1mA 100 20
Temperature
(°C)
0~70
PIN CONNECTION
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
SOP
Vcc
A15
CS2
/WE
A13
A8
A9
A11
/OE
A10
/CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A11
A9
A13
/WE
CS2
A15
Vcc
NC
A16
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
32 /OE
30 /CS1
29 DQ8
28 DQ7
27 DQ6
26 DQ5
25 DQ4
24 Vss
DQ3
22
21 DQ1
20 A0
19 A1
18 A2
17 A3
TSOP-I(Standard)
PIN DESCRIPTION
Pin Name
/CS1
CS2
/WE
/OE
A0 ~ A16
I/O1 ~ I/O8
Vcc
Vss
Pin Function
Chip Select 1
Chip Select 2
Write Enable
Output Enable
Address Input
Data Input/Output
Power(5.0V)
Ground
BLOCK DIAGRAM
A0 ROW DECODER
A16
/CS1
CS2
/OE
/WE
MEMORY ARRAY
1024x1024
I/O1
I/O8
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.05 /Feb.99
Hyundai Semiconductor
1 page  
HY628100A Series
TIMING DIAGRAM
READ CYCLE 1
ADDR
OE
CS1
tRC
tAA
tOE
tOLZ
tOH
CS2
Data
Out
High-Z
tACS
tCLZ
tOHZ
tCHZ
Data Valid
Note(READ CYCLE):
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are
not referenced to output voltage levels
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given
device and from device to device.
3. /WE is high for the read cycle.
READ CYCLE 2
ADDR
Data
Out
tAA
tOH
Previous Data
tRC
Note(READ CYCLE):
1. /WE is high for the read cycle.
2. Device is continuously selected /CS1 = VIL, CS2 = VIH.
3. /OE =VIL.
Data Valid
tOH
Rev.05 /Feb.99
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HY628100AG.PDF ] | |
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