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PDF 74ACT174 Data sheet ( Hoja de datos )
| Número de pieza | 74ACT174 | |
| Descripción | HEX D-TYPE FLIP FLOP WITH CLEAR | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74ACT174
HEX D-TYPE FLIP FLOP WITH CLEAR
s HIGH SPEED:
fMAX = 200 MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 8 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN), VIL = 0.8V (MAX)
s 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 174
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The ACT174 is an high-speed CMOS HEX
D-TYPE FLIP FLOP WITH CLEAR fabricated
with sub-micron silicon gate and double-layer
metal wiring C2MOS technology. It is ideal for low
power applications mantaining high speed
operation similar to eqivalent Bipolar Schottky
PRELIMINARY DATA
BM
(Plastic Package)
(Micro Package)
ORDER CODES :
74ACT174B
74ACT174M
TTL.
Information signals applied to D inputs are
transfered to the Q output on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independentelyof the other inputs .
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
May 1997
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1 page  
74ACT174
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf =3 ns)
Symbol
P ar ame te r
tPLH Propagation Delay Time
tPHL CK to Q
tPLH Propagation Delay Time
tPHL CLR to Q
twL CLR pulse Width, LOW
tw CK pulse Width
ts Setup Time Q to CK HIGH
or LOW
th Hold Time Q to CK HIGH
or LOW
tREM Recovery Time CLR to CK
fMAX Maximum Clock Frequency
(*) Voltage range is 5V ± 0.5V
Test Condition
V CC
(V)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
Value
TA = 25 oC
-40 to 85 oC
Min. Typ. Max. Min. Max.
1.5 7.0 10.5
11.5
Unit
ns
1.5 6.5 9.5
11.0 ns
1.5 3.0
1.5 3.0
0.5 1.5
3.5 ns
3.5 ns
1.5 ns
1.0 2.0
2.0 ns
-1.0 0.5
0.5 ns
165 200 140 MHz
CAPACITIVE CHARACTERISTICS
Symbol
P ar ame te r
Test Conditions
V CC
(V)
Value
TA = 25 oC
-40 to 85 oC
Min. Typ. Max. Min. Max.
Unit
CIN Input Capacitance
5.0
4 pF
CPD Power Dissipation
Capacitance (note 1)
5.0 fIN = 10 MHz
TBD
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to
Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD • VCC • fIN +ICC/n (per circuit)
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74ACT174.PDF ] | |
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