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74ACT174SJ PDF даташит

Спецификация 74ACT174SJ изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Hex D-Type Flip-Flop with Master Reset».

Детали детали

Номер произв 74ACT174SJ
Описание Hex D-Type Flip-Flop with Master Reset
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74ACT174SJ Даташит, Описание, Даташиты
November 1988
Revised November 1999
74AC174 74ACT174
Hex D-Type Flip-Flop with Master Reset
General Description
The AC/ACT174 is a high-speed hex D-type flip-flop. The
device is used primarily as a 6-bit edge-triggered storage
register. The information on the D inputs is transferred to
storage during the LOW-to-HIGH clock transition. The
device has a Master Reset to simultaneously clear all flip-
flops.
Features
s ICC reduced by 50%
s Outputs source/sink 24 mA
s ACT174 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC174SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150Narrow Body
74AC174SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC174PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide
74ACT174SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150Narrow
74ACT174SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT174MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT174PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide
Device also available in Tape and Reel. Specify by appending suffix lettwerwwX.D” taotatShheeoertd4Uer.cinogmcode.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0D5
CP
MR
Q0Q5
Description
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009935
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74ACT174SJ Даташит, Описание, Даташиты
Functional Description
The AC/ACT174 consists of six edge-triggered D-type flip-
flops with individual D inputs and Q outputs. The Clock
(CP) and Master Reset (MR) are common to all flip-flops.
Each D inputs state is transferred to the corresponding flip-
flops output following the LOW-to-HIGH Clock (CP) transi-
tion. A LOW input to the Master Reset (MR) will force all
outputs LOW independent of Clock or Data inputs. The AC/
ACT174 is useful for applications where the true output
only is required and the Clock and Master Reset are com-
mon to all storage elements.
Logic Diagram
Truth Table
Inputs
MR CP
LX
H
H
HL
H = HIGH Voltage Level
L = LOW Voltage Level
= LOW-to-HIGH Transition
X = Immaterial
D
X
H
L
X
Output
Q
L
H
L
Q
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ACT174SJ Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
V = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
PDIP
0.5V to +7.0V
20 mA
+20 mA
0.5V to VCC + 0.5V
20 mA
+20 mA
0.5V to V CC + 0.5V
±50 mA
±50 mA
65°C to +150°C
140°C
Recommended Operating
Conditions
Supply Voltage (VCC)
AC
2.0V to 6.0V
ACT 4.5V to 5.5V
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (V/t)
0V to VCC
0V to VCC
40°C to +85°C
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (V/t)
125 mV/ns
ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACTcircuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VCC
TA = +25°C
TA = −40°C to +85°C
(V) Typ
Guaranteed Limits
3.0 1.5
2.1
2.1
4.5 2.25 3.15
3.15
5.5 2.75 3.85
3.85
3.0 1.5
0.9
0.9
4.5 2.25 1.35
1.35
5.5 2.75 1.65
1.65
3.0 2.99
2.9
2.9
4.5 4.49
4.4
4.4
5.5 5.49
5.4
5.4
VOL Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0 0.002
4.5 0.001
5.5 0.001
2.56
3.86
4.86
0.1
0.1
0.1
2.46
3.76
4.76
0.1
0.1
0.1
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
IIN
(Note 4)
Maximum Input
Leakage Current
5.5
±0.1
±1.0
IOLD
IOHD
ICC
(Note 4)
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
75
75
4.0 40.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Units
Conditions
VOUT = 0.1V
V or VCC 0.1V
VOUT = 0.1V
V or VCC 0.1V
V IOUT = −50 µA
VIN = VIL or VIH
IOH = 12 mA
V IOH = 24 mA
IOH = 24 mA (Note 2)
V IOUT = 50 µA
VIN = VIL or VIH
IOL = 12 mA
V IOL = 24 mA
IOL = 24 mA (Note 2)
µA VI = VCC
or GND
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC
or GND
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