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74ACT273 PDF даташит

Спецификация 74ACT273 изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Octal D-Type Flip-Flop».

Детали детали

Номер произв 74ACT273
Описание Octal D-Type Flip-Flop
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74ACT273 Даташит, Описание, Даташиты
November 1988
Revised August 2000
74AC273 74ACT273
Octal D-Type Flip-Flop
General Description
The AC273 and ACT273 have eight edge-triggered D-type
flip-flops with individual D-type inputs and Q outputs. The
common buffered Clock (CP) and Master Reset (MR) input
load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D-
type input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s Q
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
s Ideal buffer for microprocessor or memory
s Eight edge-triggered D-type flip-flops
s Buffered common clock
s Buffered, asynchronous master reset
s See 377 for clock enable version
s See 373 for transparent latch version
s See 374 for 3-STATE version
s Outputs source/sink 24 mA
s 74ACT273 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC273SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74AC273SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC273PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACT273SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACT273SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT273PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
FACTis a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS009954
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74ACT273 Даташит, Описание, Даташиты
Pin Descriptions
Pin Names
D0D7
MR
CP
Q0Q7
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
Logic Diagram
Mode Select-Function Table
Operating Mode
Reset (Clear)
Load 1'
Load 0'
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Inputs
Outputs
MR CP Dn
LXX
H H
H L
Qn
L
H
L
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ACT273 Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
(PDIP)
0.5V to +7.0V
20 mA
+20 mA
0.5V to VCC + 0.5V
20 mA
+20 mA
0.5V to VCC + 0.5V
± 50 mA
± 50 mA
65°C to +150°C
140°C
Recommended Operating
Conditions
Supply Voltage (VCC)
AC
2.0V to 6.0V
ACT
4.5V to 5.5V
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (V/t)
0V to VCC
0V to VCC
40°C to +85°C
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V for AC
Minimum Input Edge Rate (V/t)
125 mV/ns
ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V for ACT
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACTcircuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VCC
TA = +25°C
TA = −40°C to +85°C
(V) Typ
Guaranteed Limits
3.0 1.5
2.1
2.1
4.5 2.25 3.15
3.15
5.5 2.75 3.85
3.85
3.0 1.5
0.9
0.9
4.5 2.25 1.35
1.35
5.5 2.75 1.65
1.65
3.0 2.99
2.9
2.9
4.5 4.49
4.4
4.4
5.5 5.49
5.4
5.4
VOL Maximum LOW Level
Output Voltage
3.0 2.56
4.5 3.86
5.5 4.86
3.0 0.002
0.1
4.5 0.001
0.1
5.5 0.001
0.1
2.46
3.76
4.76
0.1
0.1
0.1
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
IIN
(Note 4)
Maximum Input
Leakage Current
5.5
±0.1
±1.0
IOLD
IOHD
ICC
(Note 4)
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
75
75
4.0 40.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Units
Conditions
VOUT = 0.1V
V or VCC 0.1V
VOUT = 0.1V
V or VCC 0.1V
V IOUT = −50 µA
VIN = VIL or VIH
IOH = −12 mA
V IOH = −24 mA
IOH = −24 mA (Note 2)
V IOUT = 50 µA
VIN = VIL or VIH
IOL = 12 mA
V IOL = 24 mA
IOL = 24 mA (Note 2)
µA VI = VCC, GND
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC
or GND
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