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74ACT323PC PDF даташит

Спецификация 74ACT323PC изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins».

Детали детали

Номер произв 74ACT323PC
Описание 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74ACT323PC Даташит, Описание, Даташиты
June 1988
Revised October 1998
74ACT323
8-Bit Universal Shift/Storage Register with
Synchronous Reset and Common I/O Pins
General Description
The ACT323 is an 8-bit universal shift/storage register with
3-STATE outputs. Parallel load inputs and flip-flop outputs
are multiplexed to minimize pin count. Separate serial
inputs and outputs are provided for Q0 and Q7 to allow
easy cascading. Four operation modes are possible: hold
(store), shift left, shift right and parallel load.
Features
s ICC and IOZ reduced by 50%
s Common parallel I/O for reduced pin count
s Additional serial inputs and outputs for expansion
s Four operating modes: shift left, shift right, load and
store
s 3-STATE outputs for bus-oriented applications
s Outputs source/sink 24 mA
s TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACT323PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment
for DIP
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009787.prf
Pin Descriptions
Pin Name
Description
CP Clock Pulse Input
DS0
DS7
S0, S1
SR
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Synchronous Reset Input
OE1, OE2
I/O0–I/O7
3-STATE Output Enable Inputs
Multiplexed Parallel Data Inputs or
3-STATE Parallel Data Outputs
Q0, Q7
Serial Outputs
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74ACT323PC Даташит, Описание, Даташиты
Functional Description
The ACT323 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
reset, shift left, shift right, parallel load and hold operations.
The type of operation is determined by S0 and S1 as shown
in the Mode Select Table. All flip-flop outputs are brought
out through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q0 and Q7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on SR overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CP. All
Mode Select Table
other state changes are also initiated by the LOW-to-HIGH
CP transition. Inputs can change when the clock is in either
state provided only that the recommended setup and hold
times, relative to the rising edge of CP, are observed.
A HIGH signal on either OE1 or OE2 disables the 3-STATE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, load, hold and reset operations
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S0 and S1 in preparation for a paral-
lel load operation.
SR
L
H
H
H
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Inputs
S1 S0
XX
HH
LH
HL
LL
Response
CP
 Synchronous Reset; Q0–Q7 = LOW
 Parallel Load; I/OnQn
 Shift Right; DS0Q0, Q0Q1, etc.
 Shift Left; DS7Q7, Q7Q6, etc.
X Hold
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74ACT323PC Даташит, Описание, Даташиты
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3 www.fairchildsemi.com










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Номер в каталогеОписаниеПроизводители
74ACT323PC8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O PinsFairchild Semiconductor
Fairchild Semiconductor

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