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PDF 74ACT32701LB Data sheet ( Hoja de datos )
| Número de pieza | 74ACT32701LB | |
| Descripción | 16-BIT D-TYPE LATCH PULS 16-BIT BUS BUFFER WITH 3-STATE OUTPUTS (NON INVERTED) | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74ACT32701
16-BIT D-TYPE LATCH PULS 16-BIT BUS BUFFER
WITH 3-STATE OUTPUTS (NON INVERTED)
s HIGH SPEED: tPD = 4.8ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 8µA(MAX.) at TA=25°C
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), VIL = 0.8V (MAX.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 4.5V
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s FUNCTION COMPATIBLE WITH SERIES
16373 AND 16245 (244)
s IMPROVED LATCH-UP IMMUNITY
s IMPROVED ESD IMMUNITY
DESCRIPTION
The 74ACT16244 is a low voltage CMOS 16-BIT
D-TYPE LATCH and 16 BIT BUS TRANSCEIVER
with 3-STATE output non inverting fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
Both functions can be used as 16 bit or dual octal
devices, so the 16 bit transceiver can be used ad 8
bit bus buffer plus 8 bit transceiver, or only 16 bit
buffer in select direction.
LOGIC DIAGRAM
PRELIMINARY DATA
LFBGA96
(Top and Bottom view)
ORDER CODES
PACKAGE
TRAY
LFBGA96 74ACT32701LB
T&R
74ACT32701LBR
This device can be used to integrate in one chip
the internal logic component required to STV0701
to work ad P.O.D. interface in Digital TV
application. It is ideal for low power and high
speed 4.5 to 5.5. applications.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them ESD immunity and transient excess voltage.
July 2003
1/9
This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.
1 page  
74ACT32701
CAPACITIVE CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25°C
-40 to 85°C Unit
Min. Typ. Max. Min. Max.
CIN Input Capacitance
5.0
3.6 pF
COUT Output Capacitance
5.0
11 pF
CPD
Power Dissipation Capaci-
tance (note 1)
5.0
fIN = 10MHz
42
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
TEST CIRCUIT
Test
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Switch
Open
2VCC
GND
5/9
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| 74ACT32701LBR | 16-BIT D-TYPE LATCH PULS 16-BIT BUS BUFFER WITH 3-STATE OUTPUTS (NON INVERTED) | STMicroelectronics |
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