74ACT377SC PDF даташит
Спецификация 74ACT377SC изготовлена «Fairchild Semiconductor» и имеет функцию, называемую «Octal D-Type Flip-Flop with Clock Enable». |
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Детали детали
Номер произв | 74ACT377SC |
Описание | Octal D-Type Flip-Flop with Clock Enable |
Производители | Fairchild Semiconductor |
логотип |
9 Pages
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November 1988
Revised November 1999
74AC377 • 74ACT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The AC/ACT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to
the LOW-to-HIGH clock transition for predictable operation.
Features
s ICC reduced by 50%
s Ideal for addressable register applications
s Clock enable for address and data synchronization
applications
s Eight edge-triggered D-type flip-flops
s Buffered common clock
s Outputs source/sink 24 mA
s See 273 for master reset version
s See 373 for transparent latch version
s See 374 for 3-STATE version
s ACT377 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC377SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74AC377SJ
74AC377MTC
M20D
MTC20
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
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20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC377PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT377SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACT377SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT377MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT377PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
CE
Q0–Q7
CP
Description
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009961
www.fairchildsemi.com
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Logic Symbols
IEEE/IEC
Mode Select-Function Table
Operating Mode
Load ‘1'
Load ‘0'
Hold (Do Nothing)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Logic Diagram
Inputs
CP CE Dn
LH
L L
H X
XHX
Outputs
Qn
H
L
No Change
No Change
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
PDIP
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
±50 mA
±50 mA
−65°C to +150°C
140°C
Recommended Operating
Conditions
Supply Voltage (VCC)
AC
2.0V to 6.0V
ACT
4.5V to 5.5V
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
0V to VCC
0V to VCC
−40°C to +85°C
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
125 mV/ns
ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VCC
TA = +25°C
TA = −40°C to +85°C
(V) Typ
Guaranteed Limits
3.0 1.5
2.1
2.1
4.5 2.25 3.15
3.15
5.5 2.75 3.85
3.85
3.0 1.5
0.9
0.9
4.5 2.25 1.35
1.35
5.5 2.75 1.65
1.65
3.0 2.99
2.9
2.9
4.5 4.49
4.4
4.4
5.5 5.49
5.4
5.4
VOL Maximum LOW Level
Output Voltage
3.0 2.56
4.5 3.86
5.5 4.86
3.0 0.002
0.1
4.5 0.001
0.1
5.5 0.001
0.1
2.46
3.76
4.76
0.1
0.1
0.1
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
IIN Maximum Input
5.5
± 0.1
± 1.0
(Note 4) Leakage Current
IOLD
IOHD
ICC
(Note 4)
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
75
−75
4.0 40.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Units
Conditions
VOUT = 0.1V
V or VCC − 0.1V
VOUT = 0.1V
V or VCC − 0.1V
V IOUT = −50 µA
VIN = VIL or VIH
IOH = −12 mA
V IOH = −24 mA
IOH = −24 mA (Note 2)
V IOUT = 50 µA
VIN = VIL or VIH
IOL = 12 mA
V IOL = 24 mA
IOL = 24 mA (Note 2)
µA VI = VCC,
GND
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC or GND
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Номер в каталоге | Описание | Производители |
74ACT377SC | Octal D-Type Flip-Flop with Clock Enable | Fairchild Semiconductor |
74ACT377SJ | Octal D-Type Flip-Flop with Clock Enable | Fairchild Semiconductor |
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