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74ACT573SC PDF даташит

Спецификация 74ACT573SC изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Octal Latch with 3-STATE Outputs».

Детали детали

Номер произв 74ACT573SC
Описание Octal Latch with 3-STATE Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74ACT573SC Даташит, Описание, Даташиты
November 1988
Revised October 1999
74AC573 • 74ACT573
Octal Latch with 3-STATE Outputs
General Description
The 74AC573 and 74ACT573 are high-speed octal latches
with buffered common Latch Enable (LE) and buffered
common Output Enable (OE) inputs.
The 74AC573 and 74ACT573 are functionally identical to
the 74AC373 and 74ACT373 but with inputs and outputs
on opposite sides.
Features
s ICC and IOZ reduced by 50%
s Inputs and outputs on opposite sides of package allow-
ing easy interface with microprocessors
s Useful as input or output port for microprocessors
s Functionally identical to 74AC373 and 74ACT373
s 3-STATE outputs for bus interfacing
s Outputs source/sink 24 mA
s 74ACT573 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC573SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body
74AC573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC573PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT573SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body
74ACT573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT573PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
D0–D7
LE
Data Inputs
Latch Enable Input
OE 3-STATE Output Enable Input
O0–O7
3-STATE Latch Outputs
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009973
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74ACT573SC Даташит, Описание, Даташиты
Functional Description
The 74AC573 and 74ACT573 contain eight D-type latches
with 3-STATE output buffers. When the Latch Enable (LE)
input is HIGH, data on the Dn inputs enters the latches. In
this condition the latches are transparent, i.e., a latch out-
put will change state each time its D-type input changes.
When LE is LOW the latches store the information that was
present on the D-type inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE) input. When OE is
LOW, the buffers are enabled. When OE is HIGH the buff-
ers are in the high impedance mode but this does not inter-
fere with entering new data into the latches.
Truth Table
Inputs
OE LE
LH
LH
LL
HX
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
D
H
L
X
X
Outputs
On
H
L
O0
Z
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ACT573SC Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
(PDIP)
0.5V to +7.0V
20 mA
+20 mA
0.5V to VCC + 0.5V
20 mA
+20 mA
0.5V to VCC + 0.5V
±50 mA
±50 mA
65°C to +150°C
140°C
Recommended Operating
Conditions
Supply Voltage (VCC)
AC
2.0V to 6.0V
ACT
4.5V to 5.5V
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (V/t)
0V to VCC
0V to VCC
40°C to +85°C
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.0V, 4.5V, 5.5V
ACT Devices
125 mV/ns
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACTcircuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VCC
TA = +25°C
TA = −40°C to +85°C
(V) Typ
Guaranteed Limits
3.0 1.5
2.1
2.1
4.5 2.25 3.15
3.15
5.5 2.75 3.85
3.85
3.0 1.5
0.9
0.9
4.5 2.25 1.35
1.35
5.5 2.75 1.65
1.65
3.0 2.99
2.9
2.9
4.5 4.49
4.4
4.4
5.5 5.49
5.4
5.4
VOL Maximum LOW Level
Output Voltage
3.0 2.56
4.5 3.86
5.5 4.86
3.0 0.002
0.1
4.5 0.001
0.1
5.5 0.001
0.1
2.46
3.76
4.76
0.1
0.1
0.1
IIN (Note 3)
IOLD
IOHD
ICC
(Note 3)
Maximum Input Leakage Current
Minimum Dynamic
Output Current (Note 4)
Maximum Quiescent
Supply Current
IOZ Maximum 3-STATE
Leakage Current
3.0
4.5
5.5
5.5
5.5
5.5
5.5
5.5
0.36
0.36
0.36
±0.1
4.0
±0.25
0.44
0.44
0.44
±1.0
75
75
40.0
±2.5
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Units
Conditions
VOUT = 0.1V
V or VCC 0.1V
VOUT = 0.1V
V or VCC 0.1V
IOUT = −50 µA
V
VIN = VIL or VIH
V IOH = −12 mA
IOH = −24 mA
IOH = −24 mA (Note 2)
V IOUT = 50 µA
VIN = VIL or VIH
V IOL = 12 mA
IOL = 24 mA
IOL = 24 mA (Note 2)
µA VI = VCC, GND
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC or GND
VI (OE) = VIL, VIH
µA VI = VCC, GND
VO = VCC, GND
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