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PDF 74ACT574 Data sheet ( Hoja de datos )
| Número de pieza | 74ACT574 | |
| Descripción | Octal D-Type Flip-Flop with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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September 1988
Revised November 1999
74AC574 • 74ACT574
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The AC/ACT574 is a high-speed, low power octal flip-flop
with a buffered common Clock (CP) and a buffered com-
mon Output Enable (OE). The information presented to the
D-type inputs is stored in the flip-flops on the LOW-to-HIGH
Clock (CP) transition.
The AC/ACT574 is functionally identical to the AC/ACT374
except for the pinouts.
Features
s ICC and IOZ reduced by 50%
s Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
s Useful as input or output port for microprocessors
s Functionally identical to AC/ACT374
s 3-STATE outputs for bus-oriented applications
s Outputs source/sink 24 mA
s ACT574 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC574SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74AC574SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC574MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC574PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT574SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-01
74ACT574SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT574MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT574PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
D0–D7
CP
Data Inputs
Clock Pulse Input
OE 3-STATE Output Enable Input
O0–O7
3-STATE Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009910
www.fairchildsemi.com
1 page  
AC Operating Requirements for AC
Symbol
Parameter
tS Set-Up Time, HIGH or LOW
Dn to CP
tH Hold Time, HIGH or LOW
Dn to CP
tW CP Pulse Width
HIGH or LOW
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 8)
3.3
5.0
3.3
5.0
3.3
5.0
AC Electrical Characteristics for ACT
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Typ Guaranteed Minimum
0.5 2.5
3.0
0 1.5
2.0
−0.5
1.5
1.5
0 1.5
1.5
3.5 6.0
7.0
2.0 4.0
5.0
Units
ns
ns
ns
Symbol
Parameter
fMAX
Maximum Clock Frequency
tPLH Propagation Delay
CP to On
tPHL Propagation Delay
CP to On
tPZH Output Enable Time
tPZL Output Enable Time
tPHZ Output Disable Time
tPLZ Output Disable Time
Note 9: Voltage Range 5.0 is 5.0V ±0.5V
VCC
(V)
(Note 9)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
AC Operating Requirements for ACT
Min
100
2.5
2.0
2.0
2.0
2.0
2.0
TA = +25°C
CL = 50 pF
Typ
110
7.0
6.5
6.4
6.0
7.0
5.5
Max
11.0
10.0
9.5
9.0
10.5
8.5
TA = −40°C to +85°C
CL = 50 pF
Min Max
85
2.0 12.0
Units
ns
ns
1.5 11.0 ns
1.5
10.0
ns
1.5
10.0
ns
1.5 11.5 ns
1.5 9.0 ns
Symbol
Parameter
tS Set-Up Time, HIGH or LOW
Dn to CP
tH Hold Time, HIGH or LOW
Dn to CP
tW CP Pulse Width
HIGH or LOW
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
VCC
(V)
(Note 10)
5.0
TA = +25°C
CL = 50 pF
Typ
1.5
TA = −40°C to +85°C
CL = 50 pF
Guaranteed Minimum
2.5
5.0 −0.5
1.0
5.0 2.5
4.0
Units
ns
ns
ns
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ Units
Conditions
4.5
40.0
pF VCC = OPEN
pF VCC = 5.0V
5 www.fairchildsemi.com
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74ACT574.PDF ] | |
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