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PDF 74ACT646 Data sheet ( Hoja de datos )

Número de pieza 74ACT646
Descripción Octal Transceiver/Register with 3-STATE Outputs
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! 74ACT646 Hoja de datos, Descripción, Manual

November 1988
Revised December 1998
74AC646 • 74ACT646
Octal Transceiver/Register with 3-STATE Outputs
General Description
The AC/ACT646 consist of registered bus transceiver cir-
cuits, with outputs, D-type flip-flops and control circuitry
providing multiplexed transmission of data directly from the
input bus or from the internal storage registers. Data on the
A or B bus will be loaded into the respective registers on
the LOW-to-HIGH transition of the appropriate clock pin
(CPAB or CPBA). The four fundamental data handling
functions available are illustrated in Figure 1, Figure 2, Fig-
ure 3, and Figure 4.
Features
s Independent registers for A and B buses
s Multiplexed real-time and stored data transfers
s 3-STATE outputs
s 300 mil dual-in-line package
s Outputs source/sink 24 mA
s ACT646 has TTL compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC646SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74AC646SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
74ACT646SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment
for DIP and SOIC
IEEE/IEC
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010132.prf
Pin Descriptions
Pin Names
A0–A7
B0–B7
CPAB, CPBA
SAB, SBA
G
DIR
Description
Data Register A Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Input
Direction Control Input
www.fairchildsemi.com

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74ACT646 pdf
DC Electrical Characteristics for ACT
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VCC
TA = +25°C
TA = −40°C to +85°C
(V) Typ
Guaranteed Limits
4.5 1.5
2.0
2.0
5.5 1.5
2.0
2.0
4.5 1.5
0.8
0.8
5.5 1.5
0.8
0.8
4.5 4.49
4.4
4.4
5.5 5.49
5.4
5.4
VOL Maximum LOW Level
Output Voltage
4.5 3.86
5.5 4.86
4.5 0.001
0.1
5.5 0.001
0.1
3.76
4.76
0.1
0.1
IOLD
IOHD
ICC
IOZT
Maximum Input
Leakage Current
Maximum
ICC/Input
Minimum Dynamic
Output Current (Note 7)
Maximum Quiescent
Supply Current
Maximum I/O
Leakage Current
4.5 0.36
5.5 0.36
5.5 ± 0.1
5.5 0.6
5.5
5.5
5.5
8.0
5.5 ±0.6
0.44
0.44
± 1.0
1.5
75
75
80.0
±6.0
Note 6: All outputs loaded; thresholds on input associated with output under test.
Note 7: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
Units
Conditions
V VOUT = 0.1V
or VCC 0.1V
V VOUT = 0.1V
or VCC 0.1V
V IOUT = −50 µA
VIN = VIL or VIH
V IOH= 24 mA
IOH= 24 mA (Note 6)
V IOUT = 50 µA
VIN = VIL or VIH
V IOL= 24 mA
IOL = 24 mA (Note 6)
µA VI = VCC, GND
mA VI = VCC 2.1V
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC
or GND
VI (OE) = VIL, VIH
µA VI = VCC, GND
VO = VCC, GND
Symbol
Parameter
tPLH Propagation Delay
Clock to Bus
tPHL Propagation Delay
Clock to Bus
tPLH Propagation Delay
Bus to Bus
tPHL Propagation Delay
Bus to Bus
tPLH Propagation Delay
SBA or SAB to An or Bn
(w/ An or Bn HIGH or LOW)
tPHL Propagation Delay
SBA or SAB to An or Bn
(w/ An or Bn HIGH or LOW)
tPZH
Enable Time
G to An or Bn
VCC
(V)
(Note 8)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
TA = +25°C
CL = 50 pF
Min Typ Max
4.0
10.5
16.5
2.5 7.5 12.0
3.0 9.5 14.5
2.0 6.5 10.5
2.5 7.5 12.0
1.5 5.0 8.0
1.5 7.5 12.5
1.5 5.0 9.0
2.0 8.5 13.5
1.5 6.0 10.0
TA = −40°C to +85°C
CL = 50 pF
Min Max
3.0 18.5
2.0 13.0
2.5 16.0
1.5 11.5
2.0 13.5
1.0 9.0
1.5 13.5
1.0 9.5
1.5 15.5
1.5 11.0
Units
ns
ns
ns
ns
ns
3.3 1.5 8.5 13.5 1.5 15.0
5.0 1.5 6.0 10.0 1.5 11.0
ns
3.3 2.5 7.0 11.5 2.0 12.5
5.0 1.5 5.0 8.5 1.5 9.0
ns
5 www.fairchildsemi.com

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