74ACT74B PDF даташит
Спецификация 74ACT74B изготовлена «STMicroelectronics» и имеет функцию, называемую «DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR». |
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Детали детали
Номер произв | 74ACT74B |
Описание | DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR |
Производители | STMicroelectronics |
логотип |
11 Pages
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74ACT74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
s HIGH SPEED:
fMAX = 250 MHz (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN), VIL = 0.8V (MAX)
s 50Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The ACT74 is an advanced high-speed CMOS
OCTAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring C2MOS
technology.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of
BM
(Plastic Package)
(Micro Package)
ORDER CODES :
74ACT74B
74ACT74M
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriate input.
It is ideal for low power applications mantaining
high speed operation similar to equivalent Bipolar
Schottky TTL.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1997
1/11
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74ACT74
INPUT AND OUTPUT EQUIVALENT CIRCUIT
TRUTH TABLE
CLR
L
H
L
H
H
H
X: Don’t Care
INPUTS
PR
H
L
L
H
H
H
D
X
X
X
L
H
X
LOGIC DIAGRAMS
CK
X
X
X
PIN DESCRIPTION
PIN No
1, 13
2, 12
3, 11
4, 10
5, 9
6, 8
7
14
SYMBOL
1CLR,
2CLR
1D, 2D
1CK, 2CK
1PR, 2PR
1Q, 2Q
1Q, 2Q
GND
VCC
NAME AND FUNCTION
Asyncronous Reset -
Direct Input
Data Inputs
Clock Input
(LOW-to-HIGH, Edge-
Triggered)
Asyncronous Set - Direct
Input
True Flip-Flop Outputs
Complement Flip-Flop
Outputs
Ground (0V)
Positive Supply Voltage
OUT PUT S
QQ
LH
HL
HH
LH
HL
Qn Qn
F UNCT IO N
CLEAR
PRESET
NO CHANGE
This logic diagram has not be used to estimate propagation delays
2/11
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74ACT74
ABSOLUTE MAXIMUM RATINGS
Sy mb o l
Parameter
Value
Unit
VCC Supply Voltage
-0.5 to +7
V
VI DC Input Voltage
-0.5 to VCC + 0.5
V
VO DC Output Voltage
-0.5 to VCC + 0.5
V
IIK DC Input Diode Current
± 20 mA
IOK DC Output Diode Current
± 20 mA
IO DC Output Current
± 50 mA
ICC or IGND DC VCC or Ground Current
± 200
mA
Tstg Storage Temperature
-65 to +150
oC
TL Lead Temperature (10 sec)
300 oC
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Sy mb o l
P a ra met er
VCC Supply Voltage
VI Input Voltage
VO Output Voltage
Top Operating Temperature:
dt/dv Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1)
1) VIN from 0.8 V to 2.0 V
V alu e
4.5 to 5.5
0 to VCC
0 to VCC
-40 to +85
8
Unit
V
V
V
oC
ns/V
3/11
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Номер в каталоге | Описание | Производители |
74ACT74 | DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR | STMicroelectronics |
74ACT74 | Dual D-Type Positive Edge-Triggered Flip-Flop | Fairchild Semiconductor |
74ACT74 | DUAL D-TYPE FLIP FLOP | ST Microelectronics |
74ACT74 | Dual D-Type Positive Edge-Triggered Flip-Flop | Fairchild Semiconductor |
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