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Номер произв 74ACT74PC
Описание Dual D-Type Positive Edge-Triggered Flip-Flop
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 



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74ACT74PC Даташит, Описание, Даташиты
November 1988
Revised November 1999
74AC74 74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The AC/ACT74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at
a voltage level of the clock pulse and is not directly related
to the transition time of the positive-going pulse. After the
Clock Pulse input threshold voltage has been passed, the
Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Features
s ICC reduced by 50%
s Output source/sink 24 mA
s ACT74 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC74SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150Narrow Body
74AC74SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC74PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide
74ACT74SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150Narrow Body
74ACT74SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT74PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D1, D2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q1, Q2, Q2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS009920
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74ACT74PC Даташит, Описание, Даташиты
Logic Symbols
IEEE/IEC
Truth Table
(Each Half)
Inputs
Outputs
SD CD CP D
Q
Q
L H XXH L
H L XXL H
L
L
XXH
H
H H
HH
L
H H
LL
H
H H L X Q0 Q0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Q0 (Q0) = Previous Q (Q) before LOW-to-HIGH Transition of Clock
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ACT74PC Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
PDIP
0.5V to +7.0V
20 mA
+20 mA
0.5V to VCC + 0.5V
20 mA
+20 mA
0.5V to VCC + 0.5V
±50 mA
±50 mA
65°C to +150°C
140°C
Recommended Operating
Conditions
Supply Voltage (VCC)
AC
2.0V to 6.0V
ACT
4.5V to 5.5V
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (V/t)
0V to VCC
0V to VCC
40°C to +85°C
AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (V/t)
125 mV/ns
ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACTcircuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol
Parameter
VIH Minimum HIGH
Level Input
Voltage
VIL Maximum LOW
Level Input
Voltage
VOH Minimum HIGH
Level Output
Voltage
VCC
TA = +25°C
TA = −40°C to +85°C
(V) Typ
Guaranteed Limits
3.0 1.5 2.1
2.1
4.5
2.25
3.15
3.15
5.5
2.75
3.85
3.85
3.0 1.5 0.9
0.9
4.5
2.25
1.35
1.35
5.5
2.75
1.65
1.65
3.0 2.99 2.9
2.9
4.5 4.49 4.4
4.4
5.5 5.49 5.4
5.4
VOL Maximum LOW
Level Output
Voltage
3.0 2.56
4.5 3.86
5.5 4.86
3.0 0.002 0.1
4.5 0.001 0.1
5.5 0.001 0.1
2.46
3.76
4.76
0.1
0.1
0.1
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
IIN (Note 4)
IOLD
IOHD
ICC
(Note 4)
Maximum InputLeakage Current
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
± 0.1
2.0
± 1.0
75
75
20.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Units
Conditions
VOUT = 0.1V
V or VCC 0.1V
VOUT = 0.1V
V or VCC 0.1V
V IOUT = −50 µA
VIN = VIL or VIH
IOH = −12 mA
V IOH = −24 m
IOH = −24 m (Note 2)
V IOUT = 50 µA
VIN = VIL or VIH
IOL = 12 mA
V IOL = 24 mA
IOL = 24 mA (Note 2)
µA VI = VCC, GND
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC
or GND
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