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PDF 74ACT821 Data sheet ( Hoja de datos )
| Número de pieza | 74ACT821 | |
| Descripción | 10-Bit D-Type Flip-Flop with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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November 1988
Revised August 2000
74AC821 • 74ACT821
10-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The AC/ACT821 is a 10-bit D-type flip-flop with 3-STATE
outputs arranged in a broadside pinout.
Features
s 3-STATE outputs for bus interfacing
s Noninverting outputs
s Outputs source/sink 24 mA
s TTL compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC821SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74AC821SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACT821SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACT821MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT821SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tape and Reel.)
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D9
O0–O9
OE
CP
Description
Data Inputs
Data Outputs
Output Enable Input
Clock Input
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS010139
www.fairchildsemi.com
1 page  
AC Operating Requirements for AC
Symbol
Parameter
tS Setup Time, HIGH or LOW
Dn to CP
tH Hold Time, HIGH or LOW
Dn to CP
tW CP Pulse Width
HIGH or LOW
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 8)
3.3
5.0
3.3
5.0
3.3
5.0
TA = +25°C
TA = −40°C to +85°C
CL = 50 pF
CL = 50 pF
Typ Guaranteed Minimum
−1.0
1.5
1.5
−1.0
1.5
1.5
−1.0
3.5
4.0
−1.0
3.5
4.0
3.5 5.0
5.5
2.5 4.0
4.0
AC Electrical Characteristics for ACT
Symbol
Parameter
fMAX
Maximum Clock
Frequency
tPLH Propagation Delay
CP to On
tPHL Propagation Delay
CP to On
tPZH Output Enable Time
OE to On
tPZL Output Enable Time
OE to On
tPHZ Output Disable Time
OE to On
tPLZ Output Disable Time
OE to On
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 9)
5.0
TA = +25°C
CL = 50 pF
Min Typ Max
120 150
5.0 2.0 6.0 9.5
5.0 2.5 6.0 9.5
5.0 2.5
7.0 10.5
5.0 2.5
7.0 10.5
5.0 1.5
7.5 12.0
5.0 1.5
7.0 10.5
TA = −40°C to +85°C
CL = 50 pF
Min Max
110
1.5 10.5
2.0 10.5
2.0 11.5
2.0 12.0
1.0 13.0
1.0 11.5
AC Operating Requirements for ACT
Symbol
Parameter
tS Setup Time, HIGH or LOW
Dn to CP
tH Hold Time, HIGH or LOW
Dn to CP
tW CP Pulse Width
HIGH or LOW
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
VCC
(V)
(Note 10)
5.0
5.0
5.0
TA = +25°C
CL = 50 pF
Typ
TA = −40°C to +85°C
CL = 50 pF
Guaranteed Minimum
2.5 2.0
2.5
−0.5
2.0
2.5
3.0 4.5
5.5
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
35.0
Units
pF
pF
VCC = OPEN
VCC = 5.0V
Conditions
Units
ns
ns
ns
Units
MHz
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet 74ACT821.PDF ] | |
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