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74ACT825SPC PDF даташит

Спецификация 74ACT825SPC изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «8-Bit D-Type Flip-Flop».

Детали детали

Номер произв 74ACT825SPC
Описание 8-Bit D-Type Flip-Flop
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74ACT825SPC Даташит, Описание, Даташиты
July 1988
Revised September 2000
74ACT825
8-Bit D-Type Flip-Flop
General Description
The ACT825 is an 8-bit buffered register. They have Clock
Enable and Clear features which are ideal for parity bus
interfacing in high performance microprogramming sys-
tems. Also included are multiple enables that allow multi-
use control of the interface. The ACT825 has noninverting
outputs.
Features
s Outputs source/sink 24 mA
s Inputs and outputs are on opposite sides
s TTL compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74ACT825SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACT825MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACT825SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0D7
O0O7
OE1, OE2, OE3
EN
CLR
CP
Description
Data Inputs
Data Outputs
Output Enables
Clock Enable
Clear
Clock Input
FACTis a trademark of Fairchild Semiconductor.
© 2000 Fairchild Semiconductor Corporation DS009895
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74ACT825SPC Даташит, Описание, Даташиты
Functional Description
The ACT825 consists of eight D-type edge-triggered flip-
flops. These devices have 3-STATE outputs for bus sys-
tems, organized in a broadside pinning. In addition to the
clock and output enable pins, the buffered clock (CP) and
buffered Output Enable (OE) are common to all flip-flops.
The flip-flops will store the state of their individual D inputs
that meet the setup and hold time requirements on the
LOW-to-HIGH CP transition. With OE1, OE2 and OE3
LOW, the contents of the flip-flops are available at the out-
puts. When one of OE1, OE2 or OE3 is HIGH, the outputs
go to the high impedance state.
Function Table
Operation of the OE input does not affect the state of the
flip-flops. The ACT825 has Clear (CLR) and Clock Enable
(EN) pins. These pins are ideal for parity bus interfacing in
high performance systems.
When CLR is LOW and OE is LOW, the outputs are LOW.
When CLR is HIGH, data can be entered into the flip-flops.
When EN is LOW, data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition. When EN is
HIGH, the outputs do not change state, regardless of the
data or clock input transitions.
OE CLR
HX
HX
HL
LL
HH
LH
HH
HH
LH
LH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Inputs
EN
L
L
X
X
H
H
L
L
L
L
CP


X
X
X
X



Dn
L
H
X
X
X
X
L
H
L
H
Internal
Q
L
H
L
L
NC
NC
L
H
L
H
Output
O
Z
Z
Z
L
Z
NC
Z
Z
L
H
Function
High-Z
High-Z
Clear
Clear
Hold
Hold
Load
Load
Load
Load
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ACT825SPC Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC +0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC +0.5V
DC Output Voltage (VO)
DC Output Source or Sink Current
(IO)
DC VCC or Ground Current
Per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
PDIP
0.5V to 7.0V
20 mA
+20 mA
0.5V to VCC +0.5V
20 mA
+20 mA
+0.5V
± 50 mA
± 50 mA
65°C to +150°C
140°C
Recommended Operating
Conditions
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (V/t)
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
4.5V to 5.5V
0V to VCC
0V to VCC
40°C to +85°C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACTcircuits outside databook specifications.
DC Electrical Characteristics
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VCC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
TA = 25°C
TA = −40°C to +85°C
Typ Guaranteed Limits
1.5 2.0
2.0
1.5 2.0
2.0
1.5 0.8
0.8
1.5 0.8
0.8
4.49
4.4
4.4
5.49
5.4
5.4
VOL Maximum LOW Level
Output Voltage
4.5 3.86
5.5 4.86
4.5 0.001
0.1
5.5 0.001
0.1
3.76
4.76
0.1
0.1
4.5 0.36
5.5 0.36
IIN Maximum Input Leakage Current 5.5
IOZ Maximum
3-STATE Current
5.5
± 0.1
±0.5
ICCT
IOLD
IOHD
ICC
Maximum ICC/Input
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5 0.6
5.5
5.5
5.5
8.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
0.44
0.44
± 1.0
±5.0
1.5
75
75
80
Units
Conditions
V VOUT = 0.1V
or VCC 0.1V
V VOUT = 0.1V
or VCC 0.1V
V IOUT = −50 µA
VIN = VIL or VIH
V IOH = −24 mA
IOH = −24 mA (Note 2)
V IOUT = 50 µA
VIN = VIL or VIH
V IOL = 24 mA
IOL = 24 mA (Note 2)
µA VI = VCC, GND
µA VI = VIL, VIH
VO = VCC, GND
mA VI = VCC 2.1V
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC or GND
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Номер в каталогеОписаниеПроизводители
74ACT825SPC8-Bit D-Type Flip-FlopFairchild Semiconductor
Fairchild Semiconductor

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