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74ACT843SPC PDF даташит

Спецификация 74ACT843SPC изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «9-Bit Transparent Latch».

Детали детали

Номер произв 74ACT843SPC
Описание 9-Bit Transparent Latch
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74ACT843SPC Даташит, Описание, Даташиты
July 1988
Revised September 2000
74ACT843
9-Bit Transparent Latch
General Description
The ACT843 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths.
Features
s TTL compatible inputs
s 3-STATE outputs for bus interfacing
Ordering Code:
Order Number Package Number
Package Description
74ACT843SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACT843SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tape and Reel.)
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0D8
O0O8
OE
LE
CLR
PRE
Description
Data Inputs
Data Outputs
Output Enable
Latch Enable
Clear
Preset
FACTis a trademark of Fairchild Semiconductor Corporation
© 2000 Fairchild Semiconductor Corporation DS009800
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74ACT843SPC Даташит, Описание, Даташиты
Functional Description
The ACT843 consists of nine D-type latches with 3-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. This allows asynchronous
operation, as the output transition follows the data in transi-
tion. On the LE HIGH-to-LOW transition, the data that
meets the setup times is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state. In addition to
Function Tables
the LE and OE pins, the ACT843 has a Clear (CLR) pin
and a Preset (PRE) pin. These pins are ideal for parity bus
interfacing in high performance systems. When CLR is
LOW, the outputs are LOW if OE is LOW. When CLR is
HIGH, data can be entered into the latch. When PRE is
LOW, the outputs are HIGH if OE is LOW. Preset overrides
CLR.
Inputs
CLR
H
H
H
H
H
H
H
L
L
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
PRE
H
H
H
H
H
H
L
H
L
H
L
OE
H
H
H
L
L
L
L
L
L
H
H
LE
H
H
L
H
H
L
X
X
X
L
L
D
L
H
X
L
H
X
X
X
X
X
X
Internal
Q
L
H
NC
L
H
NC
H
L
H
L
H
Outputs
O
Z
Z
Z
L
H
NC
H
L
H
Z
Z
Function
High Z
High Z
Latched
Transparent
Transparent
Latched
Preset
Clear
Preset
Clear/High Z
Preset/High Z
Logic Diagram
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74ACT843SPC Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC +0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC +0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
PDIP
0.5V to +7.0V
20 mA
+20 mA
0.5V to VCC +0.5V
20 mA
+20 mA
0.5V to VCC +0.5V
±50 mA
±50 mA
65°C to +150°C
140°C
Recommended Operating
Conditions
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (V/t)
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
4.5V to 5.5V
0V to VCC
0V to VCC
40°C to +85°C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACTcircuits outside databook specifications.
DC Electrical Characteristics
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VCC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
TA = +25°C
TA = −40°C to +85°C
Typ Guaranteed Limits
1.5 2.0
2.0
1.5 2.0
2.0
1.5 0.8
0.8
1.5 0.8
0.8
4.49
4.4
4.4
5.49
5.4
5.4
VOL Maximum LOW Level
Output Voltage
4.5
5.5
4.5 0.001
5.5 0.001
3.86
4.86
0.1
0.1
3.76
4.76
0.1
0.1
4.5 0.36
5.5 0.36
IIN Maximum Input
Leakage Current
5.5
±0.1
IOZ Maximum 3-STATE
Leakage Current
5.5
±0.5
ICCT
IOLD
IOHD
ICC
Maximum
ICC/Input
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5 0.6
5.5
5.5
5.5
8.0
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
0.44
0.44
±1.0
±5.0
1.5
75
75
80.0
Units
Conditions
V VOUT = 0.1V
or VCC 0.1V
V VOUT = 0.1V
or VCC 0.1V
V IOUT = −50 µA
VIN = VIL or VIH
V IOH = −24 mA
IOH = −24 mA (Note 2)
V IOUT = 50 µA
VIN = VIL or VIH
V IO = 24 mA
IOL = 24 mA (Note 2)
µA VI = VCC, GND
µA VI = VIL, VIH
VO = VCC, GND
mA VI = VCC 2.1V
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC
or GND
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Номер в каталогеОписаниеПроизводители
74ACT843SPC9-Bit Transparent LatchFairchild Semiconductor
Fairchild Semiconductor

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