74ACTQ16374 PDF даташит
Спецификация 74ACTQ16374 изготовлена «Fairchild Semiconductor» и имеет функцию, называемую «16-Bit D-Type Flip-Flop with 3-STATE Outputs». |
|
Детали детали
Номер произв | 74ACTQ16374 |
Описание | 16-Bit D-Type Flip-Flop with 3-STATE Outputs |
Производители | Fairchild Semiconductor |
логотип |
8 Pages
No Preview Available ! |
June 1991
Revised November 1999
74ACTQ16374
16-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACTQ16374 contains sixteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte
and can be shorted together for full 16-bit operation.
The ACTQ16245 utilizes Fairchild Quiet Series technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control for superior performance.
Features
s Utilizes Fairchild FACT Quiet Series technology
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin output skew
s Buffered Positive edge-triggered clock
s Separate control logic for each byte
s 16-bit version of the ACTQ374
s Outputs source/sink 24 mA
s Additional specs for Multiple Output Switching
s Output loadings specs for both 50 pF and 250 pF loads
Ordering Code:
Order Number Package Number
Package Description
74ACTQ16374SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ16374MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbol
Pin Descriptions
Pin
Names
OEn
CPn
I0–I15
O0–O15
Description
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
Outputs
FACT, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010935
www.fairchildsemi.com
No Preview Available ! |
Functional Description
The ACTQ16374 consists of sixteen edge-triggered flip-
flops with individual D-type inputs and 3-STATE true out-
puts. The device is byte controlled with each byte function-
ing identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each byte has a buffered clock and buffered Output Enable
common to all flip-flops within that byte. The description
which follows applies to each byte. Each flip-flop will store
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CPn)
transition. With the Output Enable (OEn) LOW, the con-
tents of the flip-flops are available at the outputs. When
OEn is HIGH, the outputs go to the high impedance state.
Operation of the OEn input does not affect the state of the
flip-flops.
Truth Tables
Inputs
CP1
OE1
L
L
LL
XH
Inputs
CP2
OE2
L
L
LL
XH
H = HIGH Voltage Level
L = LOW Voltage Level
X= Immaterial
Z = HIGH Impedance
= LOW-to-HIGH Transition
I0–I7
H
L
X
X
I8–I15
H
L
X
X
Outputs
O0–O7
H
L
(Previous)
Z
Outputs
O8–O15
H
L
(Previous)
Z
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
www.fairchildsemi.com
2
No Preview Available ! |
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source/Sink Current (IO)
DC VCC or Ground Current
per Output Pin
Storage Temperature
−0.5V to +7.0V
−20 mA
+20 mA
−20 mA
+20 mA
−0.5V to VCC + 0.5V
±50 mA
± 50 mA
−65°C to +150°C
Recommended Operating
Conditions
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
4.5V to 5.5V
0V to VCC
0V to VCC
−40°C to +85°C
125 mV/ns
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C Units
Conditions
(V) Typ
Guaranteed Limits
VIH Minimum HIGH
Input Voltage
VIL Maximum LOW
Input Voltage
VOH Minimum HIGH
Output Voltage
4.5 1.5 2.0
5.5 1.5 2.0
4.5 1.5 0.8
5.5 1.5 0.8
4.5 4.49 4.4
5.5 5.49 5.4
2.0 V VOUT = 0.1V
2.0 or VCC − 0.1V
0.8 V VOUT = 0.1V
0.8 or VCC − 0.1V
4.4
5.4 V IOUT = −50 µA
VOL Maximum LOW
Output Voltage
4.5 3.86
5.5 4.86
4.5 0.001 0.1
5.5 0.001 0.1
3.76
4.76
0.1
0.1
VIN = VIL or VIH
V IOH = −24 mA
IOH = −24 mA (Note 2)
V IOUT = 50 µA
IOZ
IIN
ICCT
ICC
IOLD
IOHD
VOLP
VOLV
VOHP
Maximum 3-STATE
Leakage Current
Maximum Input Leakage Current
Maximum ICC/Input
Maximum Quiescent Supply Current
Minimum Dynamic
Output Current (Note 3)
Quiet Output Maximum
Dynamic VOL
Quiet Output
Minimum Dynamic VOL
Maximum Overshoot
4.5 0.36
5.5 0.36
5.5 ± 0.5
5.5 ± 0.1
5.5 0.6
5.5 8.0
5.5
5.0 0.5 0.8
5.0 −0.5 −1.0
5.0 VOH + 1.0 VOH + 1.5
0.44
0.44
± 5.0
± 1.0
1.5
80.0
75
−75
VIN = VIL or VIH
V IOL = 24 mA
IOL = 24 mA (Note 2)
µA VI = VIL, VIH
VO = VCC, GND
µA VI = VCC, GND
mA VI = VCC − 2.1V
µA VIN = VCC or GND
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
Figure 1, Figure 2
V
(Note 5)(Note 6)
Figure 1, Figure 2
V
(Note 5)(Note 6)
V Figure 1, Figure 2
(Note 4)(Note 6)
VOHV
Minimum VCC Droop
5.0 VOH − 1.0 VOH − 1.8
V Figure 1, Figure 2
(Note 4)(Note 6)
VIHD
Minimum HIGH Dynamic Input Voltage Level 5.0
VILD Maximum LOW Dynamic Input Voltage Level 5.0
Note 2: All outputs loaded; thresholds associated with output under test.
1.7
1.2
2.0
0.8
V (Note 4)(Note 7)
V (Note 4)(Note 7)
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Note 4: Worst case package.
Note 5: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched LOW and one output held LOW.
Note 6: Maximum number of outputs that can switch simultaneously is n. (n − 1) outputs are switched HIGH and one output held HIGH.
Note 7: Maximum number of data inputs (n) switching. (n − 1) input switching 0V to 3V (ACTQ). Input under test switching 3V to threshold (VILD).
3 www.fairchildsemi.com
Скачать PDF:
[ 74ACTQ16374.PDF Даташит ]
Номер в каталоге | Описание | Производители |
74ACTQ16373 | 16-Bit Transparent Latch with 3-STATE Outputs | Fairchild Semiconductor |
74ACTQ16373MEA | 16-Bit Transparent Latch with 3-STATE Outputs | Fairchild Semiconductor |
74ACTQ16373MTD | 16-Bit Transparent Latch with 3-STATE Outputs | Fairchild Semiconductor |
74ACTQ16374 | 16-Bit D-Type Flip-Flop with 3-STATE Outputs | Fairchild Semiconductor |
Номер в каталоге | Описание | Производители |
TL431 | 100 мА, регулируемый прецизионный шунтирующий регулятор |
Unisonic Technologies |
IRF840 | 8 А, 500 В, N-канальный МОП-транзистор |
Vishay |
LM317 | Линейный стабилизатор напряжения, 1,5 А |
STMicroelectronics |
DataSheet26.com | 2020 | Контакты | Поиск |