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74ACTQ16543MTD PDF даташит

Спецификация 74ACTQ16543MTD изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «16-Bit Registered Transceiver with 3-STATE Outputs».

Детали детали

Номер произв 74ACTQ16543MTD
Описание 16-Bit Registered Transceiver with 3-STATE Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74ACTQ16543MTD Даташит, Описание, Даташиты
December 1991
Revised December 1998
74ACTQ16543
16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ACTQ16543 contains sixteen non-inverting transceiv-
ers containing two sets of D-type registers for temporary
storage of data flowing in either direction. Each byte has
separate control inputs which can be shorted together for
full 16-bit operation. Separate Latch Enable and Output
Enable inputs are provided for each register to permit inde-
pendent input and output control in either direction of data
flow.
The ACTQ16543 utilizes Fairchild Quiet Seriestechnol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Seriesfea-
tures GTOoutput control and undershoot corrector for
superior performance.
Features
s Utilizes Fairchild FACT Quiet Series technology
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin output skew
s Independent registers for A and B buses
s Separate controls for data flow in each direction
s Back-to-back registers for storage
Multiplexed real-time and stored data transfers
s Separate control logic for each byte
s 16-bit version of the ACTQ543
s Outputs source/sink 24 mA
s Additional specs for Multiple Output Switching
s Output loading specs for both 50 pF and 250pF loads
Ordering Code:
Order Number Package Number
Package Description
74ACTQ16543SSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74ACTQ16543MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Descriptions
OEABn
OEBAn
CEABn
CEBAn
LEABn
LEBAn
A0–A15
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B0–B15
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
FACT, Quiet Series, FACT Quiet Seriesand GTOare trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010967.prf
www.fairchildsemi.com









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74ACTQ16543MTD Даташит, Описание, Даташиты
Connection Diagram
Pin Assignment for SSOP and TSSOP
Functional Description
The ACTQ16543 contains sixteen non-inverting transceiv-
ers with 3-STATE outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. The control pins may be shorted together to
obtain full 16-bit operation. The following description
applies to each byte. For data flow from A to B, for exam-
ple, the A-to-B Enable (CEABn) input must be LOW in
order to enter data from A0–A15 or take data from B0–B15,
as indicated in the Data I/O Control Table. With CEABn
LOW, a LOW signal on the A-to-B Latch Enable (LEABn)
input makes the A-to-B latches transparent; a subsequent
LOW-to-HIGH transition of the LEABn signal puts the A
latches in the storage mode and their outputs no longer
change with the A inputs. With CEABn and OEABn both
LOW, the 3-STATE B output buffers are active and reflect
the data present at the output of the A latches. Control of
data flow from B to A is similar, but using the CEBAn,
LEBAn and OEBAn inputs.
Data I/O Control Table
CEABn
H
X
L
X
L
Inputs
LEABn
X
H
L
X
X
OEABn
X
X
X
H
L
Latch Status
(Byte n)
Latched
Latched
Transparent
Output
Buffers
(Byte n)
High Z
High Z
Driving
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A-to-B data flow shown; B-to-A flow control
is the same, except using CEBAn, LEBAn and OEBAn
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74ACTQ16543MTD Даташит, Описание, Даташиты
Logic Diagrams
Byte 1 (0:7)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Номер в каталогеОписаниеПроизводители
74ACTQ16543MTD16-Bit Registered Transceiver with 3-STATE OutputsFairchild Semiconductor
Fairchild Semiconductor

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