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PDF 74ACTQ245 Data sheet ( Hoja de datos )
| Número de pieza | 74ACTQ245 | |
| Descripción | Quiet Series Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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July 1989
Revised November 1999
74ACQ245 • 74ACTQ245
Quiet Series Octal Bidirectional Transceiver
with 3-STATE Inputs/Outputs
General Description
The ACQ/ACTQ245 contains eight non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for bus-
oriented applications. Current sinking capability is 24 mA at
both the A and B ports. The Transmit/Receive (T/R) input
determines the direction of data flow through the bidirec-
tional transceiver. Transmit (active-HIGH) enables data
from A Ports to B Ports; Receive (active-LOW) enables
data from B Ports to A Ports. The Output Enable input,
when HIGH, disables both A and B ports by placing them in
a HIGH Z condition.
The ACQ/ACTQ utilizes Fairchild Quiet Series technol-
ogy to guarantee quiet output switching and improve
dynamic threshold performance. FACT Quiet Series fea-
tures GTO output control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s ICC and IOZ reduced by 50%
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Improved latch-up immunity
s 3-STATE outputs drive bus lines or buffer memory
address registers
s Outputs source/sink 24 mA
s Faster prop delays than the standard ACT245
Ordering Code:
Order Number Package Number
Package Description
74ACQ245SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACQ245SJ
M20D
20-Lead Small Outline Package (SOP) EIAJ TYPE II, 5.3mm Wide
74ACQ245PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACTQ245SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ245SJ
M20D
20-Lead Small Outline Package (SOP) EIAJ TYPE II, 5.3mm Wide
74ACTQ245QSC
MQA20
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
74ACTQ245MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ245MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ245PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010236
www.fairchildsemi.com
1 page  
AC Electrical Characteristics for ACQ
VCC
TA = +25°C
TA = −40°C to +85°C
Symbol
Parameter
(V)
CL = 50 pF
CL = 50 pF
Units
(Note 13)
Min
Typ
Max
Min
Max
tPHL Propagation Delay
3.3 2.0 7.5 10.0 2.0 10.5
tPLH Data to Output
5.0 1.5 5.0 6.5 1.5 7.0
tPZL Output Enable Time
3.3 3.0 8.5 13.0 3.0 13.5
tPZH 5.0 2.0 6.0 8.5 2.0 9.0
tPHZ Output Disable Time
3.3 1.0 8.5 14.5 1.0 15.0
tPLZ 5.0 1.0 7.5 9.5 1.0 10.0
tOSHL
Output to Output Skew (Note 14)
3.3
1.0 1.5
1.5
tOSLH
Data to Output
5.0 0.5 1.0 1.0
Note 13: Voltage Range 5.0 is 5.0V ± 0.5V
ns
ns
ns
ns
Voltage Range 3.3 is 3.3V ± 0.3V
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
AC Electrical Characteristics for ACTQ
VCC
TA = +25°C
TA = −40°C to +85°C
Symbol
Parameter
(V) CL = 50 pF
CL = 50 pF
Units
(Note 15)
Min
Typ
Max
Min
Max
tPHL Propagation Delay
tPLH Data to Output
tPZL, tPZH Output Enable Time
tPHZ, tPLZ Output Disable Time
tOSHL
Output to Output Skew (Note 16)
tOSLH
Data to Output
Note 15: Voltage Range 5.0 is 5.0V ± 0.5V
5.0 1.5 5.5 7.0 1.5 7.5 ns
5.0 2.0 7.0 9.0 2.0 9.5 ns
5.0 1.0 8.0 10.0 1.0 10.5 ns
5.0 0.5 1.0 1.0 ns
Note 16: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol
CIN
CI/O
CPD
Parameter
Input Capacitance
Input/Output Capacitance
Power Dissipation Capacitance
Typ
4.5
15
80.0
Units
pF
pF
pF
Conditions
VCC = OPEN
VCC = 5.0V
VCC = 5.0V
5 www.fairchildsemi.com
5 Page 
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
11 www.fairchildsemi.com
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet 74ACTQ245.PDF ] | |
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