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74ACTQ273SC PDF даташит

Спецификация 74ACTQ273SC изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Quiet Series Octal D-Type Flip-Flop».

Детали детали

Номер произв 74ACTQ273SC
Описание Quiet Series Octal D-Type Flip-Flop
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74ACTQ273SC Даташит, Описание, Даташиты
August 1989
Revised November 1999
74ACTQ273
Quiet Series Octal D-Type Flip-Flop
General Description
The ACTQ273 has eight edge-triggered D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) and Master Reset (MR) input load and
reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D-
type input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s Q
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
The ACTQ utilizes Fairchild Quiet Seriestechnology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Seriesfeatures
GTOoutput control and undershoot corrector in addition
to a split ground bus for superior performance.
Features
s ICC reduced by 50%
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Improved latch-up immunity
s Buffered common clock and asynchronous master reset
s Outputs source/sink 24 mA
s 4 kV minimum ESD immunity
Ordering Code:
Order Number Package Number
Package Description
74ACTQ273SC
M20B
20-Lead Small Outline Integrated Circuit, JEDEC MS-013, 0.300Wide Body
74ACTQ273SJ
M20D
20-Lead Small Outline Package, EIAJ TYPE II, 5.3mm Wide
74ACTQ273MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ273PC
N20A
20-Lead Plastic Dual-In-Line Package, JEDEC MS-001, 0.300Wide
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
Description
D0D7
MR
Data Inputs
Master Reset
CP Clock Pulse Input
Q0Q7
Data Outputs
FACT, FACT Quiet Series, and GTOare trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010585
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74ACTQ273SC Даташит, Описание, Даташиты
Logic Symbols
IEEE/IEC
Mode Select-Function Table
Operating Mode
Reset (Clear)
Load 1
Load 0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
MR
L
H
H
Logic Diagram
Inputs
CP
X


Outputs
Dn Qn
XL
HH
LL
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ACTQ273SC Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
DC Latch-up Source or
Sink Current
Junction Temperature (TJ)
PDIP
0.5V to +7.0V
20 mA
+20 mA
0.5V to VCC + 0.5V
20 mA
+20 mA
0.5V to VCC + 0.5V
±50 mA
±50 mA
65°C to +150°C
±300 mA
140°C
Recommended Operating
Conditions
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate V/t
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
4.5V to 5.5V
0V to VCC
0V to VCC
40°C to +85°C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACTcircuits outside databook specifications.
DC Electrical Characteristics
Symbol
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C Units
(V) Typ
Guaranteed Limits
Conditions
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
4.5 1.5
2.0
2.0
V VOUT = 0.1V
5.5 1.5
2.0
2.0
or VCC 0.1V
4.5 1.5
0.8
0.8
V VOUT = 0.1V
5.5 1.5
0.8
0.8
or VCC 0.1V
4.5 4.49
4.4
4.4
5.5 5.49
5.4
5.4
V IOUT = −50 µA
VOL Maximum LOW Level
Output Voltage
4.5
5.5
4.5 0.001
5.5 0.001
3.86
4.86
0.1
0.1
3.76
4.76
0.1
0.1
VIN = VIL or VIH
V IOH = −24 mA
IOH = −24 mA (Note 2)
V IOUT = 50 µA
4.5
5.5
IIN Maximum Input Leakage Current
5.5
ICCT
Maximum ICC/Input
5.5 0.6
IOLD
Minimum Dynamic
5.5
IOHD
Output Current (Note 3)
5.5
ICC Maximum Quiescent Supply Current
5.5
VOLP
Quiet Output
Maximum Dynamic VOL
5.0 1.1
VOLV
Quiet Output
Minimum Dynamic VOL
5.0 0.6
VIHD
Minimum HIGH Level Dynamic Input Voltage 5.0
1.9
VILD Maximum LOW Level Dynamic Input Voltage 5.0 1.2
Note 2: All outputs loaded; thresholds on input associated with output under test.
0.36
0.36
±0.1
4.0
1.5
1.2
2.2
0.8
0.44
0.44
± 1.0
1.5
75
75
40.0
VIN = VIL or VIH
V IOL = 24 mA
IOL = 24 mA (Note 2)
µA VI = VCC, GND
mA VI = VCC 2.1V
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC or GND
Figure 1Figure 2
V
(Note 4)
Figure 1Figure 2
V
(Note 4)
V (Note 5)
V (Note 5)
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: Max number of outputs defined as (n). n 1 Data inputs are driven 0V to 3V; one output @ GND.
Note 5: Max number of Data Inputs (n) switching. (n 1) Inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to thresh-
old (VIHD) f = 1 MHz.
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