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Спецификация 74ACTQ543QSC изготовлена «Fairchild Semiconductor» и имеет функцию, называемую «Quiet Series Octal Registered Transceiver with 3-STATE Outputs». |
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Детали детали
Номер произв | 74ACTQ543QSC |
Описание | Quiet Series Octal Registered Transceiver with 3-STATE Outputs |
Производители | Fairchild Semiconductor |
логотип |
9 Pages
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January 1990
Revised August 2000
74ACQ543• 74ACTQ543
Quiet Series Octal Registered Transceiver
with 3-STATE Outputs
General Description
The ACQ/ACTQ543 is a non-inverting octal transceiver
containing two sets of D-type registers for temporary stor-
age of data flowing in either direction. Separate Latch
Enable and Output Enable inputs are provided for each
register to permit independent input and output control in
either direction of data flow.
The ACQ/ACTQ utilizes Fairchild Quiet Series technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance FACT Quiet Series fea-
tures GTO output control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s 8-bit octal latched transceiver
s Separate controls for data flow in each direction
s Back-to-back registers for storage
s Outputs source/sink 24 mA
s 300 mil slim PDIP/SOIC
Ordering Code:
Order Number Package Number
Package Description
74ACQ543SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACQ543SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ543SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ543QSC
MQA24
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
74ACTQ543SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the order code.
Connection Diagram
Pin Descriptions
Pin Names
Description
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A0–A7
B0–B7
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS010154
www.fairchildsemi.com
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Logic Symbols
IEEE/IEC
Logic Diagram
Functional Description
The ACQ/ACTQ543 contains two sets of eight D-type
latches, with separate input and output controls for each
set. For data flow from A to B, for example, the A-to-B
Enable (CEAB) input must be LOW in order to enter data
from A0–A7 or take data from B0–B7, as indicated in the
Data I/O Control Table. With CEAB LOW, a LOW signal on
the A-to-B Latch Enable (LEAB) input makes the A-to-B
latches transparent; a subsequent LOW-to-HIGH transition
of the LEAB signal puts the A latches in the storage mode
and their outputs no longer change with the A inputs. With
CEAB and OEAB both LOW, the 3-STATE B output buffers
are active and reflect the data present at the output of the A
latches. Control of data flow from B to A is similar, but using
the CEBA, LEBA and OEBA inputs
Data I/O Control Table
Inputs
Latch Status Output Buffers
CEAB LEAB OEAB
HXX
Latched
High Z
XHX
Latched
—
L L X Transparent
—
XXH
—
High Z
LXL
—
Driving
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
DC Latch-up Source or
Sink Current
Junction Temperature (TJ)
PDIP
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
± 50 mA
± 50 mA
−65°C to +150°C
± 300 mA
140°C
Recommended Operating
Conditions
Supply Voltage VCC
ACQ
2.0V to 6.0V
ACTQ
4.5V to 5.5V
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate ∆V/∆t
0V to VCC
0V to VCC
−40°C to +85°C
ACQ Devices
VIN from 30% to 70% of VCC
VCC @3.0V, 4.5V, 5.5V
Minimum Input Edge Rate ∆V/∆t
125 mV/ns
ACTQ Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for ACQ
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VOL Maximum LOW Level
Output Voltage
IIN
(Note 4)
IOLD
IOHD
ICC
(Note 4)
IOZT
Maximum Input
Leakage Current
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
Maximum I/O
Leakage Current
VCC
TA = +25°C
TA = −40°C to +85°C
Units
(V) Typ
Guaranteed Limits
Conditions
3.0 1.5 2.1
4.5 2.25 3.15
5.5 2.75 3.85
2.1
3.15
3.85
VOUT = 0.1V
V or VCC − 0.1V
3.0 1.5 0.9
4.5 2.25 1.35
5.5 2.75 1.65
0.9
1.35
1.65
VOUT = 0.1V
V or VCC − 0.1V
3.0 2.99 2.9
2.9
4.5 4.49 4.4 4.4 V IOUT = −50 µA
5.5 5.49 5.4
5.4
3.0 2.56
4.5 3.86
5.5 4.86
3.0 0.002
0.1
2.46
3.76
4.76
0.1
VIN = VIL or VIH
IOH = −12 mA
V IOH = −24 mA
IOH = −24 mA (Note 2)
4.5 0.001
0.1
0.1
V IOUT = 50 µA
5.5 0.001
0.1
0.1
VIN = VIL or VIH
3.0
0.36
0.44
IOL = 12 mA
4.5
0.36
0.44
V IOL = 24 mA
5.5
0.36
0.44
IOL = 24 mA (Note 2)
5.5
± 0.1
± 1.0
µA VI = VCC,
GND
5.5 75 mA VOLD = 1.65V Max
5.5 −75 mA VOHD = 3.85V Min
5.5 8.0 80.0 µA VIN = VCC
or GND
VI (OE) = VIL, VIH
5.5
± 0.6
± 6.0
µA VI = VCC, GND
VO = VCC, GND
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74ACTQ543QSC | Quiet Series Octal Registered Transceiver with 3-STATE Outputs | Fairchild Semiconductor |
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