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PDF 74ACTQ563PC Data sheet ( Hoja de datos )
| Número de pieza | 74ACTQ563PC | |
| Descripción | Quiet Series Octal Latch with 3-STATE Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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January 1990
Revised December 1998
74ACTQ563
Quiet Series™ Octal Latch with 3-STATE Outputs
General Description
The ACTQ563 is a high speed octal latch with buffered
common Latch Enable (LE) and buffered common Output
Enable (OE) inputs. The ACTQ563 is functionally identical
to the ACTQ573, but with inverted outputs. The ACTQ563
utilizes Fairchild FACT Quiet Series™ technology to guar-
antee quiet output switching and improved dynamic thresh-
old performance. FACT Quiet Series features GTO™
output control and undershoot corrector in addition to a
split ground bus for superior performance.
Features
s ICC and IOZ reduced by 50%
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Improved latch-up immunity
s Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
s Outputs source/sink 24 mA
s Faster prop delays than standard ACT563
s Functionally identical to the ACTQ573 but with inverted
outputs
Ordering Code:
Order Number Package Number
Package Description
74ACTQ563PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for DIP
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
FACT™, Quiet Series™, FACT Quiet Series™ and GTO™ are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010631.prf
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
TA = +25°C
TA = −40°C to +85°C
Symbol
Parameter
VCC CL = 50 pF
CL = 50 pF
Units
(Note 7)
Min
Typ
Max
Min
Max
tPHL Propagation Delay
3.3 2.5 8.5 11.5 2.5 12.0 ns
tPLH
Dn to On
5.0 1.5 5.5 7.5 1.5 8.0
tPLH Propagation Delay
3.3 2.5 8.5 13.0 2.5 13.5 ns
tPHL
LE to On
5.0 2.0 6.0 8.5 2.0 9.0
tPZL Output Enable Time
3.3 2.5 8.5 13.0 2.5 13.5 ns
tPZH 5.0 1.5 6.0 8.5 1.5 9.0
tPHZ Output Disable Time
3.3 1.0 9.0 14.5 1.0 15.0 ns
tPLZ 5.0 1.0 6.5 9.5 1.0 10.0
tOSHL
Output to Output Skew (Note 8)
3.3
1.0 1.5
1.5 ns
tOSLH
Dn to On
5.0 0.5 1.0 1.0
Note 7: Voltage Range 5.0 is 5.0V ±0.5V and 3.3 is 3.3V ± 0.3V.
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design.
AC Operating Requirements
VCC
Symbol
Parameter
(V)
(Note 9)
tS Setup Time, HIGH or LOW
Dn to LE
tH Hold Time, HIGH or LOW
Dn to LE
tW LE Pulse Width, HIGH
3.3
5.0
3.3
5.0
3.3
5.0
Note 9: Voltage Range 5.0 is 5.0V ±0.5V and 3.3V is 3.3 ± 0.3V.
TA = +25°C
CL = 50 pF
Typ
0 3.0
0 3.0
0 1.5
0 1.5
2.0 4.0
2.0 4.0
TA = −40°C to +85°C
CL = 50 pF
Guaranteed Minimum
3.0
3.0
1.5
1.5
4.0
4.0
Units
ns
ns
ns
Capacitance
Symbol
CIN
CPD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ Units
Conditions
4.5 pF VCC = OPEN
42 pF VCC = 5.0V
5 www.fairchildsemi.com
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74ACTQ563PC.PDF ] | |
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