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74ACTQ843SC PDF даташит

Спецификация 74ACTQ843SC изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Quiet Seriesa 9-Bit Transparent Latch with 3-STATE Outputs».

Детали детали

Номер произв 74ACTQ843SC
Описание Quiet Seriesa 9-Bit Transparent Latch with 3-STATE Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74ACTQ843SC Даташит, Описание, Даташиты
March 1990
Revised December 1998
74ACTQ843
Quiet Series9-Bit Transparent Latch
with 3-STATE Outputs
General Description
The ACTQ843 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths. The
ACTQ843 utilizes Fairchild FACT Quiet Seriestechnol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTOoutput control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Inputs and outputs on opposite sides of package for
easy interface with microprocessors
s Improved latch-up immunity
s Outputs source/sink 24 mA
s ACTQ843 has TTL-compatible inputs
s Functionally and pin-compatible to AMD’s AM29843
s 3-STATE outputs for bus interfacing
Ordering Code:
Order Number Package Number
Package Description
74ACTQ843SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ843SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment for DIP and SOIC
Pin Descriptions
Pin Names
D0–D8
O0–O8
OE
LE
CLR
PRE
Description
Data Inputs
Data Outputs
Output Enable
Latch Enable
Clear
Preset
FACT, Quiet Series, FACT Quiet Seriesand GTOare trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation DS010689.prf
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74ACTQ843SC Даташит, Описание, Даташиты
Functional Description
The ACTQ843 consists of nine D-type latches with 3-
STATE outputs. The flip-flops appear transparent to the
data when Latch Enable (LE) is HIGH. This allows asyn-
chronous operation, as the output transition follows the
data in transition. On the LE HIGH-to-LOW transition, the
data that meets the setup times is latched. Data appears
on the bus when the Output Enable (OE) is LOW. When
OE is HIGH, the bus output is in the high impedance state.
Function Table
In addition to the LE and OE pins, the ACTQ843 has a
Clear (CLR) pin and a Preset (PRE) pin. These pins are
ideal for parity bus interfacing in high performance sys-
tems. When CLR is LOW, the outputs are LOW if OE is
LOW. When CLR is HIGH, data can be entered into the
latch. When PRE is LOW, the outputs are HIGH if OE is
LOW. Preset overrides CLR.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Inputs
Internal Outputs
Function
CLR PRE OE LE D
Q
O
HHHH L
L
Z High Z
HHHHH
H
Z High Z
HHHL X
NC
Z Latched
HH L H L
L
L Transparent
HH L HH
H
H Transparent
HHL L X
NC
NC Latched
HL LXX
H
H Preset
LHLXX
L
L Clear
L L LXX
H
H Preset
LHHL X
L
Z Clear/High Z
HLHLX
H
Z Preset/High Z
Logic Diagram
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74ACTQ843SC Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (I OK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
DC Latch-Up Source
or Sink Current
0.5V to +7.0V
20 mA
+20 mA
0.5V to VCC + 0.5V
20 mA
+20 mA
0.5V to VCC + 0.5V
±50 mA
±50 mA
65°C to +150°C
± 300 mA
Junction Temperature (TJ)
PDIP
140°C
Recommended Operating
Conditions
Supply Voltage (VCC)
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
Minimum Input Edge Rate V/t
4.5V to 5.5V
0V to VCC
0V to VCC
40°C to +85°C
125 mV/ns
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACTcircuits outside databook specifications.
DC Electrical Characteristics
Symbol
Parameter
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
VCC
TA = +25°C
TA = −40°C to +85°C
(V) Typ
Guaranteed Limits
4.5 1.5
2.0
2.0
5.5 1.5
2.0
2.0
4.5 1.5
0.8
0.8
5.5 1.5
0.8
0.8
4.5 4.49
4.4
4.4
5.5 5.49
5.4
5.4
VOL Maximum LOW Level
Output Voltage
4.5 3.86
5.5 4.86
4.5 0.001
0.1
5.5 0.001
0.1
3.76
4.76
0.1
0.1
IIN
IOZ
ICCT
IOLD
IOHD
ICC
VOLP
VOLV
VIHD
VILD
Maximum Input
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum ICC/Input
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
Quiet Output
Maximum Dynamic VOL
Quiet Output
Minimum Dynamic VOL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
4.5
5.5
5.5
5.5
5.5 0.6
5.5
5.5
5.5
5.0 1.1
5.0 0.6
5.0 1.9
5.0 1.2
0.36
0.36
± 0.1
± 0.5
8.0
1.5
1.2
2.0
0.8
0.44
0.44
± 1.0
± 5.0
1.5
75
75
80.0
Units
Conditions
V VOUT = 0.1V
or VCC 0.1V
V VOUT = 0.1V
or VCC 0.1V
V IOUT = −50 µA
VIN = VIL or VIH
V IOH = 24 mA
I OH = 24 mA (Note 2)
V IOUT = 50 µA
VIN = VIL or VIH
V IOL = 24 mA
IOL = 24 mA (Note 2)
µA VI = VCC, GND
µA VI = VIL, VIH
VO = VCC, GND
mA VI = VCC 2.1V
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC
or GND
V Figure 1, Figure 2
(Note 4)(Note 5)
V Figure 1, Figure 2
(Note 4)(Note 5)
V (Note 4)(Note 6)
V (Note 4)(Note 6)
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