74AHC132D PDF даташит
Спецификация 74AHC132D изготовлена «NXP Semiconductors» и имеет функцию, называемую «Quad 2-input NAND Schmitt trigger». |
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Детали детали
Номер произв | 74AHC132D |
Описание | Quad 2-input NAND Schmitt trigger |
Производители | NXP Semiconductors |
логотип |
16 Pages
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INTEGRATED CIRCUITS
DATA SHEET
74AHC132; 74AHCT132
Quad 2-input NAND Schmitt trigger
Product specification
Supersedes data of 1999 May 31
File under Integrated Circuits, IC06
1999 Sep 24
No Preview Available ! |
Philips Semiconductors
Quad 2-input NAND Schmitt trigger
Product specification
74AHC132; 74AHCT132
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V;
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
• Balanced propagation delays
• Inputs accepts voltages higher than
VCC
• For AHC only:
operates with CMOS input levels
• For AHCT only:
operates with TTL input levels
• Specified from
−40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT132 are
high-speed Si-gate CMOS devices
and are pin compatible with Low
power Schottky TTL (LSTTL). They
are specified in compliance with
JEDEC standard No. 7A.
The 74AHC/AHCT132 contain four
2-input NAND gates which accept
standard input signals. They are
capable of transforming slowly
changing input signals into sharply
defined, jitter free output signals.
The gate switches at different points
for positive and negative-going
signals. The difference between the
positive voltage VT+ and the negative
VT− is defined as the hysteresis
voltage VH.
FUNCTION TABLE
See note 1.
INPUTS
nA nB
LL
LH
HL
HH
Note
1. H = HIGH voltage level; L = LOW voltage level.
OUTPUT
nY
H
H
H
L
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
SYMBOL PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC AHCT
tPHL/tPLH propagation delay CL = 15 pF;
nA to nY
VCC = 5 V
3.3 3.5 ns
CI input capacitance VI = VCC or GND 3.0 3.0 pF
CO output capacitance
4.0 4.0 pF
CPD power dissipation CL = 50 pF; 11 14 pF
capacitance
f = 1 MHz;
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
NORTH AMERICA
74AHC132D
74AHC132PW
74AHCT132D
74AHCT132PW
74AHC132D
74AHC132PW DH
74AHCT132D
74AHCT132PW DH
PINS
14
14
14
14
PACKAGES
PACKAGE
MATERIAL
SO
TSSOP
SO
TSSOP
plastic
plastic
plastic
plastic
CODE
SOT108-1
SOT402-1
SOT108-1
SOT402-1
1999 Sep 24
2
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Philips Semiconductors
Quad 2-input NAND Schmitt trigger
PINNING
PIN
1, 4, 9 and 12
2, 5, 10 and 13
3, 6, 8 and 11
7
14
1A to 4A
1B to 4B
1Y to 4Y
GND
VCC
SYMBOL
Product specification
74AHC132; 74AHCT132
DESCRIPTION
data inputs
data inputs
data outputs
ground (0 V)
DC supply voltage
handbook, halfpage
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 VCC
13 4B
12 4A
132 11 4Y
10 3B
9 3A
8 3Y
MNA406
Fig.1 Pin configuration.
handbook, halfpage
1 1A
2 1B
1Y 3
4 2A
5 2B
2Y 6
9 3A
10 3B
3Y 8
12 4A
13 4B
4Y 11
MNA407
Fig.2 Logic symbol.
1999 Sep 24
3
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Номер в каталоге | Описание | Производители |
74AHC132 | Quad 2-input NAND Schmitt trigger | NXP Semiconductors |
74AHC132D | Quad 2-input NAND Schmitt trigger | NXP Semiconductors |
74AHC132PW | Quad 2-input NAND Schmitt trigger | NXP Semiconductors |
74AHC132PWDH | Quad 2-input NAND Schmitt trigger | NXP Semiconductors |
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