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74AHC74PWDH PDF даташит

Спецификация 74AHC74PWDH изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Dual D-type flip-flop with set and reset; positive-edge trigger».

Детали детали

Номер произв 74AHC74PWDH
Описание Dual D-type flip-flop with set and reset; positive-edge trigger
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74AHC74PWDH Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
74AHC74; 74AHCT74
Dual D-type flip-flop with set and
reset; positive-edge trigger
Product specification
Supersedes data of 1999 Aug 05
File under Integrated Circuits, IC06
1999 Sep 23









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74AHC74PWDH Даташит, Описание, Даташиты
Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product specification
74AHC74; 74AHCT74
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
Balanced propagation delays
Inputs accepts voltages higher than
VCC
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Output capability: standard
ICC category: flip-flops
Specified from
40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT74 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
No. 7A.
The 74AHC/AHCT74 dual
positive-edge triggered, D-type
flip-flops with individual data (D)
inputs, clock (CP) inputs, set (SD) and
reset (RD) inputs; also
complementary Q and Q outputs.
The set and reset are asynchronous
active LOW inputs and operate
independently of the clock input.
Information on the data input is
transferred to the Q output on the
LOW-to-HIGH transition of the clock
pulse. The D inputs must be stable
one set-up time prior to the
LOW-to-HIGH clock transition for
predictable operation.
Schmitt-trigger action in the clock
input makes the circuit highly tolerant
to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns.
SYMBOL
PARAMETER
TYPICAL
CONDITIONS
UNIT
AHC AHCT
tPHL/tPLH
fmax
CI
CPD
propagation delay
nCP to nQ, nQ
CL = 15 pF;
VCC = 5 V
3.7
nSD, nRD to nQ, nQ
3.7
max. clock frequency
130
input capacitance
VI = VCC or GND 4.0
power dissipation
capacitance
CL = 50 pF;
f = 1 MHz;
notes 1 and 2
12
3.3
3.7
100
4.0
16
ns
ns
MHz
pF
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz;
(CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
FUNCTION TABLES
Table 1 See note 1
INPUT
nSD nRD nCP
LHX
HLX
LLX
nD
X
X
X
OUTPUT
nQ nQ
HL
LH
HH
Table 2 See note 1
INPUT
OUTPUT
nSD nRD nCP
nD
nQn+1
nQn+1
HHL LH
HH HH L
Note to Tables 1 and 2
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
= LOW-to-HIGH CP transition;
Qn+1 = state after the next LOW-to-HIGH CP transition.
1999 Sep 23
2









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74AHC74PWDH Даташит, Описание, Даташиты
Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product specification
74AHC74; 74AHCT74
ORDERING INFORMATION
OUTSIDE
NORTH
AMERICA
74AHC74D
74AHC74PW
74AHCT74D
74AHCT74PW
NORTH AMERICA
74AHC74D
74AHC74PW DH
74AHCT74D
74AHCT74PW DH
TEMPERATURE
RANGE
40 to +85 °C
PINS
14
14
14
14
PACKAGE
PACKAGE
SO
TSSOP
SO
TSSOP
MATERIAL
plastic
plastic
plastic
plastic
CODE
SOT108-1
SOT402-1
SOT108-1
SOT402-1
PINNING
PIN
1 and 13
2 and 12
3 and 11
4 and 10
5 and 9
6 and 8
7
14
SYMBOL
1RD and 2RD
1D and 2D
1CP and 2CP
1SD and 2SD
1Q and 2Q
1Q and 2Q
GND
VCC
DESCRIPTION
asynchronous reset-direct input (active LOW)
data inputs
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
true flip-flop outputs
complement flip-flop outputs
ground (0 V)
DC supply voltage
handbook, halfpage
1RD 1
1D 2
1CP 3
1SD 4
1Q 5
1Q 6
GND 7
14 VCC
13 2RD
12 2D
74 11 2CP
10 2SD
9 2Q
8 2Q
MNA417
handbook, halfpage
4 10
1SD 2SD
2
12
1D
2D
D
SD
Q
1Q
2Q
3 1CP CP
11 2CP FF
1Q
Q
RD 2Q
5
9
6
8
1RD 2RD
1 13 MNA418
Fig.1 Pin configuration.
Fig.2 Logic diagram.
1999 Sep 23
3










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