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74AHCT373D PDF даташит

Спецификация 74AHCT373D изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Octal D-type transparent latch; 3-state».

Детали детали

Номер произв 74AHCT373D
Описание Octal D-type transparent latch; 3-state
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74AHCT373D Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
74AHC373; 74AHCT373
Octal D-type transparent latch;
3-state
Product specification
Supersedes data of 1998 Dec 11
File under Integrated Circuits, IC06
1999 Nov 23









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74AHCT373D Даташит, Описание, Даташиты
Philips Semiconductors
Octal D-type transparent latch; 3-state
Product specification
74AHC373; 74AHCT373
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accepts voltages higher than VCC
Common 3-state output enable input
Functionally identical to the ‘533’, ‘563’ and ‘573’
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from 40 to +85 °C and 40 to +125 °C.
DESCRIPTION
The 74AHC/AHCT373 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC/AHCT373 are octal D-type transparent
latches featuring separate D-type inputs for each latch and
3-state outputs for bus oriented applications. A Latch
Enable (LE) input and an Output Enable (OE) input are
common to all latches.
The ‘373’ consists of eight D-type transparent latches with
3-state true outputs. When LE is HIGH, data at the
Dn inputs enters the latches. In this condition the latches
are transparent, i.e. a latch output will change state each
time its corresponding D-input changes.
When LE is LOW the latches store the information that
was present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The ‘373’ is functionally identical to the ‘533’, ‘563’ and
‘573’, but the ‘533’ and ‘563’ have inverted outputs and the
‘563’ and ‘573’ have a different pin arrangement.
QUICK REFERENCE DATA
Ground = 0 V; Tamb = 25 °C; tr = tf 3.0 ns.
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
CI
CO
CPD
propagation delay
Dn to Qn; LE to Qn
input capacitance
output capacitance
power dissipation
capacitance
CL = 15 pF; VCC = 5 V
VI = VCC or GND
CL = 50 pF; f = 1 MHz;
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
TYPICAL
AHC
4.3
AHCT
4.3
3.0 3.0
4.0 4.0
10 12
UNIT
ns
pF
pF
pF
1999 Nov 23
2









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74AHCT373D Даташит, Описание, Даташиты
Philips Semiconductors
Octal D-type transparent latch; 3-state
Product specification
74AHC373; 74AHCT373
FUNCTION TABLE
See note 1.
OPERATING MODES
Enable and read register
(transparent mode)
Latch and read register
Latch register and
disable outputs
OE
L
L
L
L
H
H
INPUTS
LE
H
H
L
L
X
X
INTERNAL
Dn LATCHES
LL
HH
IL
hH
XX
XX
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
Z = high-impedance OFF-state.
OUTPUTS
Q0 to Q7
L
H
L
H
Z
Z
ORDERING INFORMATION
OUTSIDE NORTH
AMERICA
74AHC373D
74AHC373PW
74AHCT373D
74AHCT373PW
NORTH AMERICA
74AHC373D
74AHC373PW DH
74AHCT373D
7AHCT373PW DH
PINS
20
20
20
20
PACKAGES
PACKAGE MATERIAL
SO
TSSOP
SO
TSSOP
plastic
plastic
plastic
plastic
CODE
SOT163-1
SOT360-1
SOT163-1
SOT360-1
PINNING
PIN
1
2, 5, 6, 9, 12, 15, 16
and 19
3, 4, 7, 8, 13, 14, 17
and 18
10
11
20
SYMBOL
OE
Q0 to Q7
D0 to D7
GND
LE
VCC
DESCRIPTION
output enable input (active LOW)
latch outputs
data inputs
ground (0 V)
latch enable input (active HIGH)
DC supply voltage
1999 Nov 23
3










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