74ALS175N PDF даташит
Спецификация 74ALS175N изготовлена «NXP Semiconductors» и имеет функцию, называемую «Quad D flip-flop». |
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Детали детали
Номер произв | 74ALS175N |
Описание | Quad D flip-flop |
Производители | NXP Semiconductors |
логотип |
8 Pages
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INTEGRATED CIRCUITS
74ALS175
Quad D flip–flop
Product specification
IC05 Data Handbook
Philips
Semiconductors
1991 Feb 08
No Preview Available ! |
Philips Semiconductors
Quad D flip-flop
Product specification
74ALS175
FEATURES
• Four edge-triggered D flip-flops
• Buffered common clock
• Buffered asynchronous master reset
• True and complementary outputs
DESCRIPTION
The 74ALS175 is a quad, edge-triggered D-type flip-flops with
individual D inputs and both Q and Q outputs. The common buffered
clock (CP) and master reset (MR) inputs load and reset (clear) all
flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
All Q outputs will be forced Low independent of clock or data inputs
by a Low voltage level on the MR input. The device is useful for
applications where both true and complement outputs are required,
and the clock and master reset are common to all storage elements.
TYPE
74ALS175
TYPICAL
fMAX
70MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
7mA
PIN CONFIGURATION
MR 1
Q0 2
Q0 3
D0 4
D1 5
Q1 6
Q1 7
GND 8
16 VCC
15 Q3
14 Q3
13 D3
12 D2
11 Q2
10 Q2
9 CP
SF00718
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
16-pin plastic DIP
74ALS175N
16-pin plastic SO
74ALS175D
DRAWING
NUMBER
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
D0 – D3
Data inputs
1.0/1.0
CP Clock Pulse input (active rising edge)
1.0/1.0
MR Master Reset input (active-Low)
1.0/1.0
Q0 – Q3
True outputs
20/80
Q0 – Q3
Complementary outputs
20/80
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
4 5 12 13
D0 D1 D2 D3
9 CP
1 MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
1
R
9
C1
4
1D
5
12
VCC = Pin 16
GND = Pin 8
2 3 7 6 10 11 15 14
SF00719
13
LOAD VALUE
HIGH/LOW
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
0.4mA/8mA
0.4mA/8mA
2
3
7
6
10
11
15
14
SF00720
1991 Feb 08
2 853–1024 01670
No Preview Available ! |
Philips Semiconductors
Quad D flip-flop
Product specification
74ALS175
LOGIC DIAGRAM
CP 9
VCC = Pin 16
GND = Pin 8
1
MR
D0 D1 D2 D3
4 5 12 13
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP Q
RD
32
Q0 Q0
67
Q1 Q1
11 10
Q2 Q2
14 15
Q3 Q3
FUNCTION TABLE
INPUTS
OUTPUTS
MR CP D Qn Qn
LXXLH
H↑ hHL
H↑ I LH
NOTES:
H = High-voltage level
h = High state must be present one setup time before the Low-to-High clock transition
L = Low-voltage level
l = Low state must be present one setup time before the Low-to-High clock transition
X = Don’t care
↑ = Low-to-High clock transition
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
PARAMETER
VCC
VIN
IIN
VOUT
IOUT
Tamb
Tstg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VCC
VIH
VIL
IIK
IOH
IOL
Tamb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
OPERATING
MODE
Reset (clear)
Load “1”
Load “0”
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to VCC
16
0 to +70
–65 to +150
LIMITS
MIN NOM MAX
4.5 5.0 5.5
2.0
0.8
–18
–0.4
8
0 +70
SF00721
UNIT
V
V
mA
V
mA
°C
°C
UNIT
V
V
V
mA
mA
mA
°C
1991 Feb 08
3
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Номер в каталоге | Описание | Производители |
74ALS175 | Quad D flip-flop | NXP Semiconductors |
74ALS175D | Quad D flip-flop | NXP Semiconductors |
74ALS175N | Quad D flip-flop | NXP Semiconductors |
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