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74ALS374D PDF даташит

Спецификация 74ALS374D изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Latch/flip-flop».

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Номер произв 74ALS374D
Описание Latch/flip-flop
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74ALS374D Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74ALS373/74ALS374
Latch/flip–flop
Product specification
IC05 Data Handbook
Philips
Semiconductors
1991 Feb 08









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74ALS374D Даташит, Описание, Даташиты
Philips Semiconductors
Latch/flip-flop
Product specification
74ALS373/74ALS374
74ALS373 Octal transparent latch (3-State)
74ALS374 Octal D flip-flop (3-State)
FEATURES
8-bit transparent latch – 74ALS373
8-bit positive edge triggered register – 74ALS374
3-State output buffers
Common 3-State output register
Independent register and 3-State buffer operation
TYPE
TYPICAL
PROPAGATION DELAY
74ALS373
6.0ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
14mA
TYPE
74ALS374
TYPICAL
fMAX
50MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
17mA
ORDERING INFORMATION
DESCRIPTION
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
DRAWING
NUMBER
20-pin plastic DIP 74ALS373N, 74ALS374N SOT146-1
20-pin plastic SOL 74ALS373D, 74ALS374D SOT163-1
20-pin plastic SSOP
Type II
74ALS373DB, 74ALS374DB
SOT339-1
DESCRIPTION
The 74ALS373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is High. The latch remains transparent to the data
input while E is High, and stores the data that is present one setup
time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is Low, latched or
transparent data appears at the output.
When OE is High, the outputs are in High impedance “off” state,
which means they will neither drive nor load the bus.
The 74ALS374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the register operation. When OE is Low, the data in
the register appears at the outputs. When OE is High, the outputs
are in High impedance “off” state, which means they will neither
drive nor load the bus.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
D0 – D7
Data inputs
1.0/1.0
E (74ALS373)
Enable input (active-High)
1.0/1.0
OE Output enable inputs (active-Low)
1.0/1.0
CP (74ALS374)
Clock pulse input (active rising edge)
1.0/1.0
Q0 – Q7
3-State outputs
130/240
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOAD VALUE
HIGH/LOW
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
2.6mA/24mA
1991 Feb 08
2 853–1243 01670









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74ALS374D Даташит, Описание, Даташиты
Philips Semiconductors
Latch/flip-flop
Product specification
74ALS373/74ALS374
PIN CONFIGURATION – 74ALS373
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 E
LOGIC SYMBOL – 74ALS373
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11 E
1 OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC = Pin 20
GND = Pin 10
2 5 6 9 12 15 16 19
IEC/IEEE SYMBOL – 74ALS373
1
EN1
11 EN2
3 2D 1
4
7
8
13
14
17
18
2
5
6
9
12
15
16
19
SF00250
SF00251
SF00252
PIN CONFIGURATION – 74ALS374
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
LOGIC SYMBOL – 74ALS374
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11 CP
1 OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC = Pin 20
GND = Pin 10
2 5 6 9 12 15 16 19
IEC/IEEE SYMBOL – 74ALS374
1
EN1
11 C1
3 2D 1
4
7
8
13
14
17
18
2
5
6
9
12
15
16
19
SF00253
SF00254
SC00098
1991 Feb 08
3










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