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74ALS573B PDF даташит

Спецификация 74ALS573B изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Latch flip-flop».

Детали детали

Номер произв 74ALS573B
Описание Latch flip-flop
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74ALS573B Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74ALS573B/74ALS574A
Latch flip–flop
Product specification
IC05 Data Handbook
1991 Feb 08
Philips
Semiconductors









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74ALS573B Даташит, Описание, Даташиты
Philips Semiconductors
Latch/flip-flop
Product specification
74ALS573B/74ALS574A
74ALS573B Octal transparent latch (3-State)
74ALS574A Octal D flip-flop (3-State)
FEATURES
74ALS573B is broadside pinout version of 74ALS373
74ALS574A is broadside pinout version of 74ALS374
Inputs and outputs on opposite side of package allow easy
interface to microprocessors
Useful as an input or output port for microprocessors
3-State outputs for bus interfacing
Common output enable
74ALS563A and 74ALS564A are inverting version of 74ALS573B
and 74ALS574A respectively
DESCRIPTION
The 74ALS573B is an octal transparent latch coupled to eight
3-State output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
The 74ALS573B is functionally identical to the 74ALS373 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is High. The latch remains transparent to the data
input while E is High, and stores the data that is present one setup
time before the High-to-Low enable transition.
The 74ALS574A is functionally identical to the 74ALS374 but has a
broadside pinout configuration to facilitate PC board layout and
allow easy interface with microprocessors.
It is an 8-bit edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is Low, latched or
transparent data appears at the output.
When OE is High, the outputs are in high impedance “off” state,
which means they will neither drive nor load the bus.
TYPE
74ALS573B
74ALS574A
TYPICAL
PROPAGATION
DELAY
5.0ns
6.0ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
12mA
15mA
ORDERING INFORMATION
DESCRIPTION
20-pin plastic DIP
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
74ALS573BN, 74ALS574AN
DRAWING
NUMBER
SOT146-1
20-pin plastic SOL 74ALS573BD, 74ALS574AD SOT163-1
20-pin plastic SSOP
Type II
74ALS573BDB,
74ALS574ADB
SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
D0 – D7
Data inputs
1.0/1.0
E (74ALS573B)
Latch enable input
1.0/1.0
OE Output Enable input (active-Low)
1.0/1.0
CP (74ALS574A)
Clock pulse input (active rising edge)
1.0/2.0
Q0 – Q7
Data outputs
130/240
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOAD VALUE
HIGH/LOW
20µA/0.2mA
20µA/0.1mA
20µA/0.1mA
20µA/0.2mA
2.6mA/24mA
1991 Feb 08
2 853–1307 01670









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74ALS573B Даташит, Описание, Даташиты
Philips Semiconductors
Latch/flip-flop
Product specification
74ALS573B/74ALS574A
PIN CONFIGURATION – 74ALS573B
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 E
LOGIC SYMBOL – 74ALS573B
SF01073
2 3456789
D0 D1 D2 D3 D4 D5 D6 D7
11 E
1 OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC=Pin 20
GND=Pin 10
19 18 17 16 15 14 13 12
SF01075
IEC/IEEE SYMBOL – 74ALS573B
1
EN1
11
EN2
2 2D 1
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
SF01077
PIN CONFIGURATION – 74ALS574A
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 CP
LOGIC SYMBOL – 74ALS574A
SF01074
2 3456789
D0 D1 D2 D3 D4 D5 D6 D7
11 CP
1 OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC=Pin 20
GND=Pin 10
19 18 17 16 15 14 13 12
SF01076
IEC/IEEE SYMBOL – 74ALS574A
1 EN1
11
C2
2 2D 1
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
SF01078
1991 Feb 08
3










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