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74ALVC162334A PDF даташит

Спецификация 74ALVC162334A изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «16-bit registered driver with inverted register enable and 30ohm termination resistors 3-State».

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Номер произв 74ALVC162334A
Описание 16-bit registered driver with inverted register enable and 30ohm termination resistors 3-State
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74ALVC162334A Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74ALVC162334A
16-bit registered driver with inverted
register enable and 30termination
resistors (3-State)
Product specification
Replaces datasheet 74ALVC162334 of 1999 Oct 24
IC24 Data Handbook
2000 Mar 14
Philips
Semiconductors









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74ALVC162334A Даташит, Описание, Даташиты
Philips Semiconductors
16-bit registered driver with inverted register enable
and 30termination resistors (3-State)
Product specification
74ALVC162334A
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
Output drive capability 50 transmission lines @ 85°C
Current drive ±24 mA at 3.0 V
Integrated 30 termination resistors
Input diodes to accommodate strong drivers
DESCRIPTION
The 74ALVC162334A is an 16-bit universal bus driver. Data flow is
controlled by active low output enable (OE), active low latch enable
(LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is
HIGH and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
The 74ALVC162334A is designed with 30 series resistors in both
HIGH or LOW output stages.
When OE is LOW the outputs are active. When OE is HIGH, the
outputs go to the high impedance OFF-state. Operation of the OE
input does not affect the state of the latch/flip -flop.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
PIN CONFIGURATION
OE
Y1
Y2
GND
Y3
Y4
VCC
Y5
Y6
GND
Y7
Y8
Y9
Y10
GND
Y11
Y12
VCC
Y13
Y14
GND
Y15
Y16
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 CP
47 A1
46 A2
45 GND
44 A3
43 A4
42 VCC
41 A5
40 A6
39 GND
38 A7
37 A8
36 A9
35 A10
34 GND
33 A11
32 A12
31 VCC
30 A13
29 A14
28 GND
27 A15
26 A16
25 LE
SH00198
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
tPHL/tPLH
Propagation delay
An to Yn;
LE to Yn;
CP to Yn
VCC = 3.3 V, CL = 50 pF
2.9
3.5
3.3
fmax Maximum clock frequency
VCC = 3.3 V, CL = 50 pF
240
CI Input capacitance
4.0
CI/O Input/Output capacitance
8.0
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
transparent mode
Output enabled
Output disabled
Clocked mode
Output enabled
Output disabled
10
3
21
15
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
UNIT
ns
MHz
pF
pF
pF
2000 Mar 14
2 853-2197 23314









No Preview Available !

74ALVC162334A Даташит, Описание, Даташиты
Philips Semiconductors
16-bit registered driver with inverted register enable
and 30termination resistors (3-State)
Product specification
74ALVC162334A
ORDERING INFORMATION
PACKAGES
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
PIN DESCRIPTION
PIN NUMBER
24
2, 3, 5, 6, 8, 9, 11, 12, 13,
14, 16, 17, 19, 20, 22, 23
10, 15, 21, 28, 34, 45
7, 22, 35, 50
1
25
48
26, 27, 29, 30, 32, 37,
38, 40, 41, 43, 44, 46, 47
SYMBOL
NC
Y1 to Y18
GND
VCC
OE
LE
CP
A1 to A18
NAME AND FUNCTION
No connection
Data outputs
Ground (0V)
Positive supply voltage
Output enable input
(active LOW)
Latch enable input
(active LOW)
Clock input
Data inputs
LOGIC SYMBOL (IEEE/IEC)
OE 1
CP 48
LE 25
Y1 2
Y2 3
Y3 5
Y4 6
Y5 8
Y6 9
Y7 11
Y8 12
Y9 13
Y10 14
Y11 16
Y12 17
Y13 19
Y14 20
Y15 21
Y16 23
EN1
2C3
C3
G2
1 1 3D
47 A1
46 A2
44 A3
43 A4
41 A5
40 A6
38 A7
37 A8
36 A9
35 A10
33 A11
32 A12
30 A13
29 A14
27 A15
26 A16
SH00199
TEMPERATURE
RANGE
–40°C to +85°C
ORDER CODE
74ALVC162334A DGG
LOGIC SYMBOL
OE
CP
LE
A0 D
LE
CP
DRAWING
NUMBER
SOT364-1
Y0
TO THE 17 OTHER CHANNELS
SH00157
TYPICAL INPUT (DATA OR CONTROL)
VCC
A1
SH00200
FUNCTION TABLE
INPUTS
OE LE CP
HXX
OUTPUTS
AY
XZ
LLXL
L
L LXH
H
LH
LH
L HH
LHL
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High impedance “off” state
= LOW-to-HIGH level transition
L
H
X
X
L
H
Y01
Y02
NOTES:
1. Output level before the indicated steady-state input conditions
were established, provided that CP is high before LE goes low.
2. Output level before the indicated steady-state input conditions
were established.
2000 Mar 14
3










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