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74ALVC162374 PDF даташит

Спецификация 74ALVC162374 изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in Outputs».

Детали детали

Номер произв 74ALVC162374
Описание Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74ALVC162374 Даташит, Описание, Даташиты
October 2001
Revised October 2001
74ALVC162374
Low Voltage 16-Bit D-Type Flip-Flop
with 3.6V Tolerant Inputs and Outputs
and 26Series Resistors in Outputs
General Description
The ALVC162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and output enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
The ALVC162374 is also designed with 26series resis-
tors in the outputs. This design reduces line noise in appli-
cations such as memory address drivers, clock drivers and
bus transceivers/transmitters.
The 74ALVC162374 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74ALVC162374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26series resistors in outputs
s tPD (CLK to On)
3.9 ns max for 3.0V to 3.6V VCC
5.3 ns max for 2.3V to 2.7V VCC
9.6 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Uses patented noise/EMI reduction circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Descriptions
74ALVC162374T
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
CPn
I0I15
O0O15
Description
Output Enable Input (Active LOW)
Clock Pulse Input
Inputs
Outputs
© 2001 Fairchild Semiconductor Corporation DS500688
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74ALVC162374 Даташит, Описание, Даташиты
Connection Diagram
Truth Tables
Inputs
Outputs
CP1
OE1
I0–I7
O0–O7
LHH
L L L
L L X O0
XHX Z
Inputs
Outputs
CP2
OE2
L
I8–I15
H
O8–O15
H
L L L
LLX
XHX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
O0 = Previous O0 before HIGH-to-LOW of CP
O0
Z
Functional Description
The 74ALVC162374 consists of sixteen edge-triggered flip-
flops with individual D-type inputs and 3-STATE true out-
puts. The device is byte controlled with each byte function-
ing identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each clock has a buffered clock and buffered Output
Enable common to all flip-flops within that byte. The
description which follows applies to each byte. Each flip-
Logic Diagram
flop will store the state of their individual I inputs that meet
the setup and hold time requirements on the LOW-to-HIGH
Clock (CPn) transition. With the Output Enable (OEn) LOW,
the contents of the flip-flops are available at the outputs.
When OEn is HIGH, the outputs go to the high impedance
state. Operations of the OEn input does not affect the state
of the flip-flops.
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ALVC162374 Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC)
DC Input Voltage (VI)
Output Voltage (VO) (Note 3)
DC Input Diode Current (IIK)
VI < 0V
DC Output Diode Current (IOK)
VO < 0V
DC Output Source/Sink Current
(IOH/IOL)
DC VCC or GND Current per
Supply Pin (ICC or GND)
Storage Temperature Range (TSTG)
0.5V to +4.6V
0.5V to 4.6V
0.5V to VCC +0.5V
50 mA
50 mA
±50 mA
±100 mA
65°C to +150°C
Recommended Operating
Conditions (Note 4)
Power Supply
Operating
1.65V to 3.6V
Input Voltage
Output Voltage (VO)
Free Air Operating Temperature (TA)
Minimum Input Edge Rate (t/V)
0V to VCC
0V to VCC
40°C to +85°C
VIN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The Recommended Operating Conditionstable will define the condi-
tions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
Symbol
Parameter
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
VOH HIGH Level Output Voltage
VOL LOW Level Output Voltage
II
IOZ
ICC
ICC
Input Leakage Current
3-STATE Output Leakage
Quiescent Supply Current
Increase in ICC per Input
Conditions
IOH = −100 µA
IOH = −2 mA
IOH = −4 mA
IOH = −6 mA
IOH = −8 mA
IOH = −12 mA
IOL = 100 µA
IOL = 2 mA
IOL = 4 mA
IOL = 6 mA
IOL = 8 mA
IOL = 12 mA
0 VI 3.6V
0 VO 3.6V
VI = VCC or GND, IO = 0
VIH = VCC 0.6V
VCC Min Max
(V)
1.65 - 1.95 0.65 x VCC
2.3 - 2.7
1.7
2.7 - 3.6
2.0
1.65 - 1.95
2.3 - 2.7
0.35 x VCC
0.7
2.7 - 3.6
0.8
1.65 - 3.6 VCC - 0.2
1.65
1.2
2.3 1.9
2.3 1.7
3 2.4
2.7 2
3.0 2
1.65 - 3.6
0.2
1.65
0.45
2.3 0.4
2.3 0.55
3 0.55
2.7 0.6
3 0.8
3.6 ±5.0
3.6 ±10
3.6 40
3 - 3.6
750
Units
V
V
V
V
µA
µA
µA
µA
3 www.fairchildsemi.com










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