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PDF 74ALVC162838T Data sheet ( Hoja de datos )
| Número de pieza | 74ALVC162838T | |
| Descripción | Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs/Outputs and 26 Series Resistors in the Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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November 2001
Revised November 2001
74ALVC162838
Low Voltage 16-Bit Selectable Register/Buffer
with 3.6V Tolerant Inputs/Outputs
and 26Ω Series Resistors in the Outputs
General Description
The ALVC162838 contains sixteen non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CLK) sig-
nals. The device operates in a 16-bit word wide mode. All
outputs can be placed into 3-State through the use of the
OE pin. These devices are ideally suited for buffered or
registered 168 pin and 200 pin SDRAM DIMM memory
modules.
The 74ALVC162838 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The ALVC162838 is also designed with 26Ω series resis-
tors in the outputs. This design reduces line noise in appli-
cations such as memory address drivers, clock drivers, and
bus transceivers/transmitters.
The 74ALVC162838 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s Compatible with PC100 and PC133 DIMM module
specifications
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26Ω series resistors in the outputs
s tPD (CLK to On)
4.4 ns max for 3.0V to 3.6V VCC
5.9 ns max for 2.3V to 2.7V VCC
9.8 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Uses patented noise/EMI reduction circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor. The minimum
value of the resistor is determined by the current -sourcing capability of the
driver.
Ordering Code:
Ordering Code Package Number
Package Descriptions
74ALVC162838T
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
I0–I15
O0–O15
CLK
REGE
Description
Output Enable Input (Active LOW)
Inputs
Outputs
Clock Input
Register Enable Input
© 2001 Fairchild Semiconductor Corporation DS500711
www.fairchildsemi.com
1 page  
AC Loading and Waveforms
TABLE 1. Values for Figure 1
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
SWITCH
Open
VL
GND
FIGURE 1. AC Test Circuit
TABLE 2. Variable Matrix
(Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω)
Symbol
Vmi
Vmo
VX
VY
VL
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
6V
2.7V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
6V
VCC
2.5V ± 0.2V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
VCC*2
1.8V ± 0.15V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
VCC*2
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
trec Waveforms
FIGURE 6. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
5 www.fairchildsemi.com
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| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74ALVC162838T.PDF ] | |
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