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74ALVC16373MTD PDF даташит

Спецификация 74ALVC16373MTD изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs».

Детали детали

Номер произв 74ALVC16373MTD
Описание Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74ALVC16373MTD Даташит, Описание, Даташиты
October 2001
Revised October 2001
74ALVC16373
Low Voltage 16-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch
Enable (LE) is HIGH. When LE is LOW, the data that meets
the setup time is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
outputs are in a high impedance state.
The 74ALVC16373 is designed for low voltage (1.1V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74ALVC16373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.1V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD (In to On)
3.5 ns max for 3.0V to 3.6V VCC
3.9 ns max for 2.3V to 2.7V VCC
6.8 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Support live insertion and withdrawal (Note 1)
s Uses patented noise/EMI reduction circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74ALVC16373GX
(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
74ALVC16373MTD
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS500687
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74ALVC16373MTD Даташит, Описание, Даташиты
Connection Diagrams
Pin Assignment for TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
Pin Names
OEn
LEn
I0I15
O0O15
NC
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
No Connect
FBGA Pin Assignments
12
A O0 NC
B O2 O1
C O4 O3
D O6 O5
E O8 O7
F O10 O9
G O12 O11
H
O14
O13
J O15 NC
Truth Tables
3
OE1
NC
VCC
GND
GND
GND
VCC
NC
OE2
4
LE1
NC
VCC
GND
GND
GND
VCC
NC
LE2
5
NC
I1
I3
I5
I7
I9
I11
I13
NC
6
I0
I2
I4
I6
I8
I10
I12
I14
I15
Inputs
LE1 OE1 I0–I7
XHX
HL L
HLH
LLX
Inputs
LE2
OE2
I8–I15
XHX
HL L
HLH
LLX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
O0 = Previous O0 before HIGH-to-LOW of Latch Enable
Outputs
O0–O7
Z
L
H
O0
Outputs
O8–O15
Z
L
H
O0
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74ALVC16373MTD Даташит, Описание, Даташиты
Functional Description
The 74ALVC16373 contains sixteen edge D-type latches
with 3-STATE outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
the In enters the latches. In this condition the latches are
transparent, i.e., a latch output will change state each time
Logic Diagram
its I input changes. When LEn is LOW, the latches store
information that was present on the I inputs a setup time
preceding the HIGH-to-LOW transition on LEn. The
3-STATE outputs are controlled by the Output Enable
(OEn) input. When OEn is LOW the standard outputs are in
the 2-state mode. When OEn is HIGH, the standard outputs
are in the high impedance mode but this does not interfere
with entering new data into the latches.
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ALVC16373MTDLow Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and OutputsFairchild Semiconductor
Fairchild Semiconductor

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