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PDF 74ALVC16501MTD Data sheet ( Hoja de datos )
| Número de pieza | 74ALVC16501MTD | |
| Descripción | Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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October 2001
Revised October 2001
74ALVC16501
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16501 is an 18-bit universal bus transceiver
which combines D-type latches and D-type flip-flops to
allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the LOW-to-HIGH
transition of CLKAB. When OEAB is HIGH, the outputs are
active. When OEAB is LOW, the outputs are in a high-
impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
The ALVC16501 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
The ALVC16501 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD (A to B, B to A)
3.4 ns max for 3.0V to 3.6V VCC
4.0 ns max for 2.3V to 2.7V VCC
7.0 ns max for 1.65V to 1.95V VCC
s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Uses patented noise/EMI reduction circuitry
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OEBA should be tied to VCC through a pull-up resistor and OEAB
should be tied to GND through a pull-down resistor; the minimum value of
the resistors is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74ALVC16501MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2001 Fairchild Semiconductor Corporation DS500683
www.fairchildsemi.com
1 page  
AC Electrical Characteristics
Symbol
Parameter
fMAX
tPHL, tPLH
Maximum Clock Frequency
Propagation Delay
Bus to Bus
tPHL, tPLH Propagation Delay
CLK to Bus
tPHL, tPLH Propagation Delay
LE to Bus
tPZL, tPZH
tPLZ, tPHZ
tW
tS
tH
Output Enable Time
Output Disable Time
Pulse Width
Setup Time
Hold Time
T A = −40°C to +85°C, RL = 500Ω
CL = 50 pF
CL = 30 pF
V CC = 3.3V ± 0.3V
V CC = 2.7V
V CC = 2.5V ± 0.2V V CC = 1.8V ± 0.15V
Min Max Min Max Min Max Min Max
250 200 200 100
1.1 3.4 1.3 4.0 0.8 3.5 1.5 7.0
1.1 4.0 1.3 4.9 0.8 4.4 1.5 8.8
1.1 4.3 1.3 5.4 0.8 4.9 1.5 9.8
1.1 4.3 1.3 5.4 0.8 4.9 1.5 9.8
1.3 4.2 1.3 4.7 0.8 4.2 0.8 7.6
1.5 1.5 1.5 4.0
1.5 1.5 1.5 2.5
1.0 1.0 1.0 1.0
Capacitance
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
Parameter
Conditions
CIN
COUT
CPD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Outputs Enabled
VI = 0V or VCC
VI = 0V or VCC
f = 10 MHz, CL = 50 pF
TA = +25°C
VCC Typical
3.3 6
3.3 7
3.3 20
2.5 20
Units
pF
pF
pF
5 www.fairchildsemi.com
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet 74ALVC16501MTD.PDF ] | |
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