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74ALVC16835 PDF даташит

Спецификация 74ALVC16835 изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs».

Детали детали

Номер произв 74ALVC16835
Описание Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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74ALVC16835 Даташит, Описание, Даташиты
September 2001
Revised February 2002
74ALVC16835
Low Voltage 18-Bit Universal Bus Driver
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16835 low voltage 18-bit universal bus driver
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (In) to Ouputs (On) on a
Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
The 74ALVC16835 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O capability up to 3.6V.
The 74ALVC16835 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s Compatible with PC100 DIMM module specifications
s 1.65V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD (CLK to On)
4.5 ns max for 3.0V to 3.6V VCC
5.5 ns max for 2.3V to 2.7V VCC
9.2 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Latchup conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model >200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC (OE to GND) through a pulldown resistor;
the minimum value of the resistor is determined by the current sourcing
capability of the driver.
Ordering Code:
Order Number
Package
Number
Package Description
74ALVC16835MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2002 Fairchild Semiconductor Corporation DS500645
www.fairchildsemi.com









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74ALVC16835 Даташит, Описание, Даташиты
Connection Diagram
Logic Diagram
Pin Descriptions
Pin Names
OE
LE
CLK
I1 - I18
O1 - O18
NC
Description
Output Enable Input (Active LOW)
Latch Enable Input
Clock Input
Data Inputs
3-STATE Outputs
No Connect
Truth Table
Inputs
Outputs
OE LE CLK In
On
HXXX
Z
L HX L
L
L HXH
H
LLL
L
L L H
H
L L H X O0 (Note 2)
L L L X O0 (Note 3)
H = Logic HIGH
L = Logic LOW
X = Dont Care, but not floating
Z = High Impedance
↑ = LOW-to-HIGH Clock Transition
Note 2: Output level before the indicated steady-state input conditions
were established provided that CLK was HIGH before LE went LOW.
Note 3: Output level before the indicated steady-state input conditions
were established.
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74ALVC16835 Даташит, Описание, Даташиты
Absolute Maximum Ratings(Note 4)
Supply Voltage (VCC)
DC Input Voltage (VI)
Output Voltage (VO) (Note 5)
DC Input Diode Current (IIK)
VI < 0V
DC Output Diode Current (IOK)
VO < 0V
DC Output Source/Sink Current
(IOH/IOL)
DC VCC or GND Current per
Supply Pin (ICC or GND)
Storage Temperature Range (TSTG)
0.5V to +4.6V
0.5V to 4.6V
0.5V to VCC +0.5V
50 mA
50 mA
±50 mA
±100 mA
65°C to +150°C
Recommended Operating
Conditions (Note 6)
Power Supply
Operating
1.65V to 3.6V
Input Voltage (VI)
Output Voltage (VO)
Free Air Operating Temperature (TA)
Minimum Input Edge Rate (t/V)
0V to VCC
0V to VCC
40°C to +85°C
VIN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 4: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The Recommended Operating Conditionstable will define the condi-
tions for actual device operation.
Note 5: IO Absolute Maximum Rating must be observed, limited to 4.6V.
Note 6: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
Symbol
Parameter
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
VOH HIGH Level Output Voltage
VOL LOW Level Output Voltage
II
IOZ
ICC
ICC
Input Leakage Current
3-STATE Output Leakage
Quiescent Supply Current
Increase in ICC per Input
Conditions
IOH = −100 µA
IOH = −4 mA
IOH = −6 mA
IOH = −12 mA
IOH = −24 mA
IOL = 100 µA
IOL = 4 mA
IOL = 6 mA
IOL = 12 mA
IOL = 24 mA
0 VI 3.6V
0 VO 3.6V
VI = VCC or GND, IO = 0
VIH = VCC 0.6V
VCC
Min Max
(V)
1.65 - 1.95 0.65 x VCC
2.3 - 2.7
1.7
2.7 - 3.6
2.0
1.65 - 1.95
2.3 - 2.7
0.35 x VCC
0.7
2.7 - 3.6
0.8
1.65 - 3.6 VCC - 0.2
1.65
1.2
2.3 2.0
2.3 1.7
2.7 2.2
3.0 2.4
3.0 2
1.65 - 3.6
0.2
1.65
0.45
2.3 0.4
2.3 0.7
2.7 0.4
3.0 0.55
3.6 ±5.0
3.6 ±10
3.6 40
3 - 3.6
750
Units
V
V
V
V
µA
µA
µA
µA
3 www.fairchildsemi.com










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