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74ALVC16835A PDF даташит

Спецификация 74ALVC16835A изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «18-bit registered driver 3-State».

Детали детали

Номер произв 74ALVC16835A
Описание 18-bit registered driver 3-State
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74ALVC16835A Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74ALVC16835A
18-bit registered driver (3-State)
Product specification
Replaces datasheet 74ALVC16835 of 1999 Mar 18
IC24 Data Handbook
2000 Mar 14
Philips
Semiconductors









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74ALVC16835A Даташит, Описание, Даташиты
Philips Semiconductors
18-bit registered driver (3-State)
Product specification
74ALVC16835A
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
Output drive capability 50 transmission lines @ 85°C
Input diodes to accommodate strong drivers
DESCRIPTION
The 74ALVC16835A is a 18–bit registered driver. Data flow is
controlled by active low output enable (OE), active low latch enable
(LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is
HIGH and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
When OE is LOW the outputs are active. When OE is HIGH, the
outputs go to the high impedance OFF–state. Operation of the OE
input does not affect the state of the latch/flip-flop.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
PIN CONFIGURATION
NC
NC
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 GND
55 NC
54 A1
53 GND
52 A2
51 A3
50 VCC
49 A4
48 A5
47 A6
46 GND
45 A7
44 A8
43 A9
42 A10
41 A11
40 A12
39 GND
38 A13
37 A14
36 A15
35 VCC
34 A16
33 A17
32 GND
31 A18
30 CP
29 GND
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
SH00188
TYPICAL
tPHL/tPLH
Propagation delay
An to Yn;
LE to Yn;
CP to Yn
VCC = 3.3 V, CL = 50 pF
2.3
2.6
2.5
fmax Maximum clock frequency
VCC = 3.3 V, CL = 50 pF
350
CI Input capacitance
4.0
CI/O Input/Output capacitance
8.0
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
transparent mode
Output enabled
Output disabled
Clocked mode
Output enabled
Output disabled
13
3
22
15
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
UNIT
ns
MHz
pF
pF
pF
2000 Mar 14
2 853–2190 23314









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74ALVC16835A Даташит, Описание, Даташиты
Philips Semiconductors
18-bit registered driver (3-State)
Product specification
74ALVC16835A
ORDERING INFORMATION
PACKAGES
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
PIN DESCRIPTION
PIN NUMBER
1, 2, 55
3, 5, 6, 8, 9, 10, 12, 13,
14, 15, 16, 17, 19, 20,
21, 23, 24, 26
4, 11, 18, 25, 32, 39, 46,
53, 56
7, 22, 35, 50
27
28
30
54, 52, 51, 49, 48, 47,
45, 44, 43, 42, 41, 40,
38, 37, 36, 34, 33, 31
SYMBOL NAME AND FUNCTION
NC No connection
Y1 to Y18 Data outputs
GND
VCC
OE
LE
CP
Ground (0V)
Positive supply voltage
Output enable input
(active LOW)
Latch enable input
(active LOW)
Clock input
A1 to A18 Data inputs
TEMPERATURE
RANGE
–40°C to +85°C
ORDER CODE
74ALVC16835A DGG
LOGIC SYMBOL
DRAWING
NUMBER
SOT364-1
OE
CP
LE
A1 D
LE Y1
CP
TO THE 17 OTHER CHANNELS
SH00203
TYPICAL INPUT (DATA OR CONTROL)
VCC
A1
SH00200
2000 Mar 14
3










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