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74ALVC574PW PDF даташит

Спецификация 74ALVC574PW изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «Octal D-type flip-flop positive edge-trigger 3-state».

Детали детали

Номер произв 74ALVC574PW
Описание Octal D-type flip-flop positive edge-trigger 3-state
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74ALVC574PW Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
DATA SHEET
74ALVC574
Octal D-type flip-flop; positive
edge-trigger; 3-state
Product specification
2002 Mar 04









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74ALVC574PW Даташит, Описание, Даташиты
Philips Semiconductors
Octal D-type flip-flop; positive edge-trigger;
3-state
Product specification
74ALVC574
FEATURES
Wide supply voltage range from 1.65 to 3.6 V
Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
ESD protection:
2000 V Human Body Model (JESD22-A114-A)
200 V Machine Model (JESD22-A115-A).
DESCRIPTION
The 74ALVC574 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
The 74ALVC574 is an octal D-type flip-flop featuring
separate D-type inputs for each flip-flop and 3-state
outputs for bus oriented applications. A clock (CP) input
and an output enable (OE) input are common to all
flip-flops.
The eight flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the eight flip-flops is
available at the outputs. When OE is HIGH, the outputs go
to the high-impedance OFF-state. Operation of the
OE input does not affect the state of the flip-flops.
The ‘574’ is functionally identical to the ‘374’, but the ‘374’
has a different pin arrangement.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
PARAMETER
tPHL/tPLH propagation delay CP to Qn
CI input capacitance
CPD power dissipation capacitance per buffer
CONDITIONS
VCC = 1.8 V; CL = 30 pF; RL = 1 k
VCC = 2.5 V; CL = 30 pF; RL = 500
VCC = 2.7 V; CL = 50 pF; RL = 500
VCC = 3.3 V; CL = 50 pF; RL = 500
VCC = 3.3 V; notes 1 and 2
outputs enabled
outputs disabled
TYPICAL UNIT
3.1 ns
2.3 ns
2.5 ns
2.5 ns
3.5 pF
21 pF
13 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
2002 Mar 04
2









No Preview Available !

74ALVC574PW Даташит, Описание, Даташиты
Philips Semiconductors
Octal D-type flip-flop; positive edge-trigger;
3-state
Product specification
74ALVC574
ORDERING INFORMATION
TYPE NUMBER
74ALVC574D
74ALVC574PW
PINS
20
20
PACKAGES
PACKAGE
SO
TSSOP
MATERIAL
plastic
plastic
CODE
SOT163-1
SOT360-1
FUNCTION TABLE
See note 1.
OPERATING MODES
Load and read register
Latch and read register
OE
L
L
H
H
INPUT
CP
INTERNAL
Dn FLIP-FLOPS
lL
hH
lL
hH
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition;
L = LOWvoltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition;
= LOW-to-HIGH clock transition;
Z = high-impedance OFF-state.
OUTPUT
Q0 to Q7
L
H
Z
Z
PINNING
PIN
1 OE
2, 3, 4, 5, 6, 7, 8, 9
10
Q0 to Q7
GND
11 CP
12, 13, 14, 15, 16, 17, 18, D7 to D0
19
20 VCC
SYMBOL
DESCRIPTION
output enable input (active LOW)
3-state flip-flop output
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
data input
supply voltage
2002 Mar 04
3










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