74ALVC74PW PDF даташит
Спецификация 74ALVC74PW изготовлена «NXP Semiconductors» и имеет функцию, называемую «Dual D-type flip-flop with set and reset; positive-edge trigger». |
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Детали детали
Номер произв | 74ALVC74PW |
Описание | Dual D-type flip-flop with set and reset; positive-edge trigger |
Производители | NXP Semiconductors |
логотип |
20 Pages
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INTEGRATED CIRCUITS
DATA SHEET
74ALVC74
Dual D-type flip-flop with set and
reset; positive-edge trigger
Product specification
Supersedes data of 2003 Jan 24
2003 May 26
No Preview Available ! |
Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product specification
74ALVC74
FEATURES
• Wide supply voltage range from 1.65 to 3.6 V
• Complies with JEDEC standard:
JESD8-7 (1.65 to 1.95 V)
JESD8-5 (2.3 to 2.7 V)
JESD8B/JESD36 (2.7 to 3.6 V).
• 3.6 V tolerant inputs/outputs
• CMOS low power consumption
• Direct interface with TTL levels (2.7 to 3.6 V)
• Power-down mode
• Latch-up performance exceeds 250 mA
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
DESCRIPTION
The 74ALVC74 is a dual positive-edge triggered, D-type
flip-flop with individual data (D), clock (CP), set (SD) and
reset (RD) inputs and complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C.
SYMBOL
PARAMETER
tPHL/tPLH propagation delay nCP to nQ, nQ
tPHL/tPLH propagation delay nSD, nRD to nQ, nQ
fmax maximum clock frequency
CI input capacitance
CPD power dissipation capacitance per buffer
CONDITIONS
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω
VCC = 3.3 V; CL = 50 pF; RL = 500 Ω
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω
VCC = 2.7 V; CL = 50 pF; RL = 500 Ω
VCC = 3.3 V; CL = 50 pF; RL = 500 Ω
VCC = 3.3 V; notes 1 and 2
TYPICAL UNIT
3.7 ns
2.6 ns
2.8 ns
2.7 ns
3.5 ns
2.5 ns
3.1 ns
2.3 ns
425 MHz
3.5 pF
35 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
2003 May 26
2
No Preview Available ! |
Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive-edge trigger
ORDERING INFORMATION
TYPE NUMBER
74ALVC74D
74ALVC74PW
74ALVC74BQ
TEMPERATURE
RANGE
−40 to +85 °C
−40 to +85 °C
−40 to +85 °C
PINS
14
14
14
PACKAGE
PACKAGE
SO14
TSSOP14
DHVQFN14
FUNCTION TABLES
Table 1 See note 1
nSD
L
H
L
nRD
H
L
L
INPUT
nCP
X
X
X
Table 2 See note 1
INPUT
nSD
H
H
nRD
H
H
nCP
↑
↑
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH CP transition;
Qn+1 = state after the next LOW-to-HIGH transition of CP.
nD
X
X
X
nD
L
H
Product specification
74ALVC74
MATERIAL
plastic
plastic
plastic
CODE
SOT108-1
SOT402-1
SOT762-1
OUTPUT
nQ nQ
HL
LH
HH
OUTPUT
nQn+1
L
H
nQn+1
H
L
2003 May 26
3
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