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74ALVCH162827 PDF даташит

Спецификация 74ALVCH162827 изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «20-bit buffer/line driver/ non-inverting/with 30ohm termination resistors (3-State)».

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Номер произв 74ALVCH162827
Описание 20-bit buffer/line driver/ non-inverting/with 30ohm termination resistors (3-State)
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74ALVCH162827 Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74ALVCH162827
20-bit buffer/line driver, non-inverting,
with 30W termination resistors (3-State)
Product specification
IC24 Data Handbook
1998 Sep 29
Philips
Semiconductors









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74ALVCH162827 Даташит, Описание, Даташиты
Philips Semiconductors
20-bit buffer/line driver, non-inverting, with 30
termination resistors (3-State)
Product specification
74ALVCH162827
FEATURES
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive ± 12 mA at 3.0 V
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
Integrated 30 W termination resistors
DESCRIPTION
The 74ALVCH162827 high-performance CMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ALVCH162827 20-bit buffers provide high performance bus
interface buffering for wide data/address paths or buses carrying
parity. They have NAND Output Enables (nOE1, nOE2) for
maximum control flexibility.
The 74ALVCH162827 is designed with 30series resistance in both
the pull-up and pull-down output structures. This design reduces line
noise in applications such as memory address drivers, clock drivers
and bus receivers/transmitters.
To ensure the high impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf = 2.5ns
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
CI
CPD
Propagation delay
nAn to nYn
Input capacitance
Power dissipation capacitance per latch
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
VI = GND to VCC1
Output enabled
Output disabled
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in mW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL × VCC2 × fo) = sum of outputs.
TYPICAL
2.9
2.9
5
14
3
UNIT
ns
pF
pF
ORDERING INFORMATION
PACKAGES
56-Pin Plastic TSSOP Type II
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
–40°C to +85°C
74ALVCH162827DGG
NORTH AMERICA
ACH162827DGG
DWG NUMBER
SOT364-1
PIN DESCRIPTION
PIN NUMBER
55, 54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
2, 3, 5, 6, 8, 9, 10, 12, 13, 14,
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1, 56,
28, 29
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
SYMBOL
1A0 - 1A9
2A0 - 2A9
1Y0 - 1Y9
2Y0 - 2Y9
1OE1 1OE2,
2OE1, 2OE2
GND
VCC
Data inputs
FUNCTION
Data outputs
Output enable inputs (active-LOW)
Ground (0V)
Positive supply voltage
1998 Sep 29
2 853-2127 20100









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74ALVCH162827 Даташит, Описание, Даташиты
Philips Semiconductors
20-bit buffer/line driver, non-inverting, with 30
termination resistors (3-State)
Product specification
74ALVCH162827
PIN CONFIGURATION
1OE1
1Y0
1Y1
GND
1Y2
1Y3
VCC
1Y4
1Y5
1Y6
GND
1Y7
1Y8
1Y9
2Y0
2Y1
2Y2
GND
2Y3
2Y4
2Y5
VCC
2Y6
2Y7
GND
2Y8
2Y9
2OE1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 1OE2
55 1A0
54 1A1
53 GND
52 1A2
51 1A3
50 VCC
49 1A4
48 1A5
47 1A6
46 GND
45 1A7
44 1A8
43 1A9
42 2A0
41 2A1
40 2A2
39 GND
38 2A3
37 2A4
36 2A5
35 VCC
34 2A6
33 2A7
32 GND
31 2A8
30 2A9
29 2OE2
SH00010
LOGIC SYMBOL (IEEE/IEC)
1OE1 1
1OE2 56
2OE1 28
2OE2 29
1A0 55
54
1A1
52
1A2
51
1A3
1A4 49
1A5 48
47
1A6
1A7 45
1A8 44
1A9 43
2A0 42
2A1 41
2A2 40
2A3 38
2A4 37
2A5 36
2A6 34
2A7 33
2A8 31
2A9 30
&
EN1
&
EN2
1 1
1 2
2 1Y0
3 1Y1
5 1Y2
6 1Y3
8 1Y4
9 1Y5
10 1Y6
12 1Y7
13 1Y8
14 1Y9
15 2Y0
16 2Y1
17 2Y2
19 2Y3
20 2Y4
21 2Y5
23 2Y6
24 2Y7
26 2Y8
27 2Y9
SH00012
LOGIC SYMBOL
55 54 52 51 49 48 47 45 44 43
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9
1 1OE1
56 1OE2
1Y0 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 1Y9
2 3 5 6 8 9 10 12 13 14
42 41 40 38 37 36 34 33 31 30
2A0 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 2A9
28 2OE1
29 2OE2
2Y0 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 2Y9
15 16 17 19 20 21 23 24 26 27
SH00011
FUNCTION TABLE
INPUTS
OUTPUT
nOE1 nOE2 nAn
nYn
LLL
L
L LH
H
HXX
Z
XHX
Z
X = Don’t care
Z = High impedance “off” state
H = High voltage level
L = Low voltage level
OPERATING MODE
Transparent
Transparent
High impedance
High impedance
1998 Sep 29
3










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