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74ALVCH16843DGG PDF даташит

Спецификация 74ALVCH16843DGG изготовлена ​​​​«NXP Semiconductors» и имеет функцию, называемую «18-bit bus-interface D-type latch 3-State».

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Номер произв 74ALVCH16843DGG
Описание 18-bit bus-interface D-type latch 3-State
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 

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74ALVCH16843DGG Даташит, Описание, Даташиты
INTEGRATED CIRCUITS
74ALVCH16843
18-bit bus-interface D-type latch (3-State)
Product specification
IC24 Data Handbook
1998 Aug 04
Philips
Semiconductors









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74ALVCH16843DGG Даташит, Описание, Даташиты
Philips Semiconductors
18-bit bus interface D-type latch (3-State)
Product specification
74ALVCH16843
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
All data inputs have bus hold
Output drive capability 50transmission lines @ 85°C
DESCRIPTION
The 74ALVCH16843 has two 9–bit D-type latch featuring separate
D-type inputs for each latch and 3-State outputs for bus oriented
applications. The two sections of each register are controlled
independently by the latch enable (nLE), clear (nCLR),
preset (nPRE) and output enable (nOE) control gates.
When nOE is LOW, the data in the registers appear at the outputs.
When nOE is HIGH, the outputs are in the high impedance OFF
state. Operation of the nOE input does not affect the state of the
flip-flops.
The 74ALVCH16843 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
PIN CONFIGURATION
1CLR
1OE
1Q0
GND
1Q1
1Q2
VCC
1Q3
1Q4
1Q5
GND
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
VCC
2Q6
2Q7
GND
2Q8
2OE
2CLR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 1LE
55 1PRE
54 1D0
53 GND
52 1D1
51 1D2
50 VCC
49 1D3
48 1D4
47 1D5
46 GND
45 1D6
44 1D7
43 1D8
42 2D0
41 2D1
40 2D2
39 GND
38 2D3
37 2D4
36 2D5
35 VCC
34 2D6
33 2D7
32 GND
31 2D8
30 2PRE
29 2LE
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf 2.5ns
SYMBOL
PARAMETER
CONDITIONS
SH00143
TYPICAL
tPHL/tPLH
CI
Propagation delay
nDn to nQn
Propagation delay
nLE to nQn
Input capacitance
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
transparent mode
Output enabled
Output disabled
Clocked mode
Output enabled
Output disabled
2.2
2.1
2.3
2.0
5.0
17
3
19
9
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
UNIT
ns
ns
pF
pF
ORDERING INFORMATION
PACKAGES
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
TEMPERATURE
RANGE
–40°C to +85°C
OUTSIDE NORTH
AMERICA
74ALVCH16843 DGG
NORTH AMERICA
ACH16843 DGG
DRAWING
NUMBER
SOT364-1
1998 Aug 04
2 853–2108 019833









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74ALVCH16843DGG Даташит, Описание, Даташиты
Philips Semiconductors
18-bit bus interface D-type latch (3-State)
Product specification
74ALVCH16843
PIN DESCRIPTION
PIN NUMBER
SYMBOL
1 1CLR
2 1OE
55 1PRE
56 1LE
54, 52, 51, 49, 48,
47, 45, 44, 43
3, 5, 6, 8, 9,
10, 12, 13, 14
4, 11, 18, 25,
32, 39, 46, 53
7, 22, 35, 50
27
1D0 to 1D8
1Q0 to 1Q8
GND
VCC
2OE
28 2CLR
29 2LE
30
42, 41, 40, 38, 37,
36, 34, 33, 31
15, 16, 17, 19, 20,
21, 23, 24, 26
2PRE
2D0 to 2D8
2Q0 to 2Q8
NAME AND FUNCTION
Clear input (active LOW)
Output enable input (active
LOW)
Preset input (active LOW)
Latch enable input (active
HIGH)
Data inputs
Data outputs
Ground (0V)
Positive supply voltage
Output enable input (active
LOW)
Clear input (active LOW)
Latch enable input (active
HIGH)
Preset input (active LOW)
Data inputs
Data outputs
FUNCTION TABLE
INPUTS
nPRE nCLR nOE
LE
LXLX
HL LX
HH L H
HH L H
HH L H
XXHH
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High impedance “off” state
OUTPUT
DX Q
XH
XL
LL
HH
X Q0
XZ
LOGIC SYMBOL
1 55 2 56
1CLR 1PRE 1OE 1LE
3 1Q0
1D0
5 1Q1
1D1
6 1Q2
1D2
8 1Q3
1D3
9 1Q4
1D4
10 1Q5
1D5
12 1Q6
1D6
13 1Q7
1D7
14 1Q8
1D8
15 2Q0
16 2Q1
17 2Q2
19 2Q3
20 2Q4
21 2Q5
23 2Q6
24 2Q7
26 2Q8
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2CLR 2PRE 2OE 2LE
28 30 27 29
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
SH00144
1998 Aug 04
3










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