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PDF 74ALVT16899 Data sheet ( Hoja de datos )
| Número de pieza | 74ALVT16899 | |
| Descripción | 2.5V/3.3V 18-bit latched transceiver with 16-bit parity generator/checker 3-State | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
74ALVT16899
2.5V/3.3V 18-bit latched transceiver with
16-bit parity generator/checker (3-State)
Product specification
IC23 Data Handbook
1998 Jun 30
Philips
Semiconductors
1 page  
Philips Semiconductors
2.5V/3.3V 18-bit latched transceiver with 16-bit parity
generator/checker (3-State)
Product specification
74ALVT16899
BLOCK DIAGRAM
9–bit
Transparent
Latch
OE
9–bit
Output
Buffer
OEB
LEA
A0
A1
A2
A3
A4
A5
A6
A7
APAR
OEA
SEL
LE
Parity
Generator
1
mux
0
9–bit
Output
Buffer
OE
1
mux Parity
0 Generator
9–bit
Transparent
Latch
LE
ODD/
EVEN
(1 of 2 parity blocks)
FUNCTION TABLE
INPUTS
OEB OEA SEL LEA
HHXX
HL L L
HL LH
HL LX
HLHX
H L HH
LHLH
LHLH
LHL L
L HHH
L HHH
L LXX
H = High voltage level
L = Low voltage level
X = Don’t care
LEB
X
H
H
L
H
H
X
H
X
L
H
X
OPERATING MODE
3-State A bus and B bus (input A & B simultaneously)
B → A, transparent B latch, generate parity from B0 - B7, check B bus parity
B → A, transparent A & B latch, generate parity from B0 - B7, check A & B bus parity
B → A, B bus latched, generate parity from latched B0 - B7 data, check B bus parity
B → A, transparent B latch, parity feed-through, check B bus parity
B → A, transparent A & B latch, parity feed-through, check A & B bus parity
A → B, transparent A latch, generate parity from A0 - A7, check A bus parity
A → B, transparent A & B latch, generate parity from A0 - A7, check A & B bus parity
A → B, A bus latched, generate parity from latched A0 - A7 data, check A bus parity
A → B, transparent A latch, parity feed-through, check A bus parity
A → B, transparent A & B latch, parity feed-through, check A & B bus parity
Output to A bus and B bus (NOT ALLOWED)
1998 Jun 30
5
B0
B1
B2
B3
B4
B5
B6
B7
BPAR
LEB
ERRA
ERRB
SH00084
5 Page 
Philips Semiconductors
2.5V/3.3V 18-bit latched transceiver with 16-bit parity
generator/checker (3-State)
Product specification
74ALVT16899
AC WAVEFORMS
VM = 1.5V or VCC/2 whichever is less; VIN = GND to 3.0V
nAx INPUT
VM
tPHL
nYx OUTPUT
VM
VM
tPLH
3.0V or VCC,
whichever is less
0
VOH
VM
VOL
SW00160
Waveform 1. Input (nAx) to Output (nYx) Propagation Delays
1
SEL
nOE
INPUT
VM
tPZL
VM
tPLZ
3.0V or VCC
whichever is
less
0V
nYx
OUTPUT
tPZH
VM
nYx
OUTPUT
VM
tPHZ
VX
VOL
VOH
VY
0V
SW00204
Waveform 2. 3-State Output Enable and Disable Times
An, APAR
(Bn, BPAR)
VM VM
INPUT
Bn, BPAR
(An, APAR)
tPLH
VM
tPHL
VM
OUTPUT
SA00293
Waveform 3. Propagation Delay, An to Bn, Bn to An, APAR to BPAR, BPAR to APAR
SEL
ODD/EVEN
0
0
LEA
(LEB)
1
An
(Bn) ODD PARITY VM
BPAR
(APAR)
tPHL
EVEN PARITY
VM
VM
ODD PARITY
INPUT
tPLH
VM OUTPUT
NOTE: Only even parity mode is shown, odd parity mode would be with ODD/EVEN = 1
SA00294
Waveform 4. Propagation Delay, An to BPAR or Bn to APAR
1998 Jun 30
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet 74ALVT16899.PDF ] | |
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