74AUC1G00 PDF даташит
Спецификация 74AUC1G00 изготовлена «NXP Semiconductors» и имеет функцию, называемую «Single 2-input NAND gate». |
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Детали детали
Номер произв | 74AUC1G00 |
Описание | Single 2-input NAND gate |
Производители | NXP Semiconductors |
логотип |
12 Pages
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INTEGRATED CIRCUITS
DATA SHEET
74AUC1G00
Single 2-input NAND gate
Preliminary specification
File under Integrated Circuits, IC24
2002 Nov 12
No Preview Available ! |
Philips Semiconductors
Single 2-input NAND gate
Preliminary specification
74AUC1G00
FEATURES
• Wide supply voltage range from 0.8 to 2.7 V
• Performance optimised for VCC = 1.8 V
• High noise immunity
• Complies with JEDEC standard:
– JESD76 (1.65 to 1.95 V)
• 8 mA output drive (VCC = 1.65 V)
• CMOS low power consumption
• Latch-up performance exceeds 250 mA
• ESD protection:
2000 V Human Body Model (A 114-A)
200 V Machine Model (A 115-A)
• 3.3 V tolerant inputs/outputs
• SC-88A and SC-74A package.
DESCRIPTION
The 74AUC1G00 is a high-performance, low-power,
low-voltage, Si-gate CMOS device.
Schmitt-trigger action at all inputs makes the circuit
tolerant for slower input rise and fall time.
This device is fully specified for partial power-down
applications using Ioff. The Ioff circuitry disables the output,
preventing the damaging current backflow through the
device when it is powered down.
The 74AUC1G00 provides the single 2-input NAND
function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; input slewrate ≥ 1 V/ns.
SYMBOL
PARAMETER
tPHL/tPLH propagation delay inputs A and B to
output Y
CI input capacitance
CPD power dissipation capacitance per buffer
CONDITIONS
VCC = 0.8 V; CL = 15 pF; RL = 2 kΩ
VCC = 1.2 V; CL = 15 pF; RL = 2 kΩ
VCC = 1.5 V; CL = 15 pF; RL = 2 kΩ
VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ
VCC = 2.5 V; CL = 30 pF; RL = 500 Ω
VCC = 1.8 V; notes 1 and 2
TYPICAL UNIT
4.7 ns
1.8 ns
1.4 ns
1.4 ns
1.2 ns
4 pF
14 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
2002 Nov 12
2
No Preview Available ! |
Philips Semiconductors
Single 2-input NAND gate
Preliminary specification
74AUC1G00
FUNCTION TABLE
See note 1.
A
L
L
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
INPUT
B
L
H
L
H
OUTPUT
Y
H
H
H
L
ORDERING INFORMATION
TYPE NUMBER
74AUC1G00GW
74AUC1G00GV
TEMPERATURE
RANGE
−40 to +85 °C
−40 to +85 °C
PINS
5
5
PACKAGE
PACKAGE MATERIAL
SC-88A
SC-74A
plastic
plastic
CODE
SOT353
SOT753
MARKING
FA
F00
PINNING
PIN
1
2
3
4
5
SYMBOL
B
A
GND
Y
VCC
data input B
data input A
ground (0 V)
data output Y
supply voltage
DESCRIPTION
handbook, halfpage
B1
A2
GND 3
5 VCC
00
4Y
MNA096
Fig.1 Pin configuration.
2002 Nov 12
handbook, halfpage
1B
2A
Y4
MNA097
Fig.2 Logic symbol.
3
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Номер в каталоге | Описание | Производители |
74AUC1G00 | Single 2-input NAND gate | NXP Semiconductors |
74AUC1G00GV | Single 2-input NAND gate | NXP Semiconductors |
74AUC1G00GW | Single 2-input NAND gate | NXP Semiconductors |
74AUC1G02 | 74AUC1G02 Single 2-input NOR gate | Integrated Circuit Solution Inc |
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