74AVC16373 PDF даташит
Спецификация 74AVC16373 изготовлена «NXP Semiconductors» и имеет функцию, называемую «16-bit D-type transparent latch; 3.6 V tolerant; 3-state». |
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Детали детали
Номер произв | 74AVC16373 |
Описание | 16-bit D-type transparent latch; 3.6 V tolerant; 3-state |
Производители | NXP Semiconductors |
логотип |
16 Pages
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INTEGRATED CIRCUITS
DATA SHEET
74AVC16373
16-bit D-type transparent latch;
3.6 V tolerant; 3-state
Product Specification
Supersedes data of 1998 Dec 11
File under Integrated Circuits, IC24
2000 Mar 09
No Preview Available ! |
Philips Semiconductors
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
Product Specification
74AVC16373
FEATURES
• Wide supply voltage range from 1.2 to 3.6 V
• Complies with JEDEC standard no. 8-1A/5/7
• CMOS low power consumption
• Input/output tolerant up to 3.6 V
• Dynamic Controlled Output (DCO) circuit dynamically
changes output impedance, resulting in noise reduction
without speed degradation
• Low inductance multiple VCC and GND pins to minimize
noise and ground bounce
• Supports Live Insertion.
DESCRIPTION
The 74AVC16373 is a 16-bit D-type transparent latch
featuring separate D-type inputs for each latch, and
3-state outputs for bus oriented applications. One Latch
Enable (LE) input and one Output Enable (OE) input are
provided per 8-bit section. The 74AVC16373 consist of
two sections of eight D-type transparent latches with
3-state true outputs.
The 74AVC16373 is designed to have an extremely fast
propagation delay and a minimum amount of power
consumption.
To ensure the high-impedance output state during
power-up or power-down, pin OEn should be tied to VCC
through a pull-up resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is
implemented to support termination line drive during
transient (see Figs 1 and 2).
handbook, h0alfpage
I OH
(mA)
1.8 V
−100
MNA506
2.5 V
−200
3.3 V
−300
01234
VOH (V)
Fig.1 Output voltage as a function of the
HIGH-level output current.
300
handbook, halfpage
IOL
(mA)
200
3.3 V
2.5 V
100
1.8 V
MNA507
0
01234
VOL (V)
Fig.2 Output voltage as a function of the
LOW-level output current.
2000 Mar 09
2
No Preview Available ! |
Philips Semiconductors
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
Product Specification
74AVC16373
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.0 ns.
SYMBOL
PARAMETER
tPHL/tPLH
propagation delay
nDn to nQn
CI input capacitance
CPD power dissipation
capacitance per buffer
CONDITIONS
VCC = 1.2 V
VCC = 1.5 V
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
notes 1 and 2
outputs enabled
outputs disabled
TYP.
3.6
3.1
2.2
1.6
1.4
5.0
34
1
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
∑ (CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC.
UNIT
ns
ns
ns
ns
ns
pF
pF
pF
FUNCTION TABLE
See note 1.
OPERATING MODES
Enable and read register
(transparent mode)
Latch and read register
(hold mode)
Latch register and disable outputs
nOE
L
L
L
L
H
H
INPUTS
LE
H
H
L
L
L
L
nAn
L
H
l
h
l
h
INTERNAL
LATCHES
L
H
L
H
L
H
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high impedance OFF-state.
OUTPUTS
nYn
L
H
L
H
Z
Z
2000 Mar 09
3
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Номер в каталоге | Описание | Производители |
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