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PDF 74AVC16373DGG Data sheet ( Hoja de datos )
| Número de pieza | 74AVC16373DGG | |
| Descripción | 16-bit D-type transparent latch; 3.6 V tolerant; 3-state | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
74AVC16373
16-bit D-type transparent latch;
3.6 V tolerant; 3-state
Product Specification
Supersedes data of 1998 Dec 11
File under Integrated Circuits, IC24
2000 Mar 09
1 page  
Philips Semiconductors
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
Product Specification
74AVC16373
handbook, halfpage
1OE 1
1Q0 2
1Q1 3
GND 4
1Q2 5
1Q3 6
VCC 7
1Q4 8
1Q5 9
GND 10
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
VCC 18
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
48 1LE
47 1D0
46 1D1
45 GND
44 1D2
43 1D3
42 VCC
41 1D4
40 1D5
39 GND
16373
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
31 VCC
30 2D4
29 2D5
28 GND
27 2D6
26 2D7
25 2LE
MNA541
handbook, halfpage
1 24
1OE 2OE
47 1D0
46 1D1
1Q0 2
1Q1 3
44 1D2
1Q2 5
43 1D3
41 1D4
40 1D5
1Q3 6
1Q4 8
1Q5 9
38 1D6
1Q6 11
37 1D7
36 2D0
1Q7 12
2Q0 13
35 2D1
2Q1 14
33 2D2
2Q2 16
32 2D3
30 2D4
2Q3 17
2Q4 19
29 2D5
2Q5 20
27 2D6
2Q6 22
26 2D7
2Q7 23
1LE 2LE
48 25 MNA547
Fig.3 Pin configuration.
2000 Mar 09
5
Fig.4 Logic symbol.
5 Page 
Philips Semiconductors
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
Product Specification
74AVC16373
handbook, full pagewidth
nOE input
VI
GND
VCC
output
LOW-to-OFF
OFF-to-LOW
VOL
VOH
output
HIGH-to-OFF
OFF-to-HIGH
GND
VM
t PLZ
t PZL
t PHZ
VX
VY
VM
t PZH
VM
outputs
enabled
outputs
disabled
outputs
enabled
MNA478
VCC
≤2.3 to 2.7 V
3.0 to 3.6 V
VM
0.5 × VCC
0.5 × VCC
VX
VOL + 0.15 V
VOL + 0.3 V
VY
VOH − 0.15 V
VOH − 0.3 V
VI
VCC
VCC
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.9 3-state enable and disable times.
handbook, full pagewidth
VI
nDn input
GND
VI
nLE input
GND
VM
th
t su
VM
th
t su
MNA542
VCC
VM
≤2.3 to 2.7 V 0.5 × VCC
3.0 to 3.6 V 0.5 × VCC
VI
VCC
VCC
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.10 Data set-up and hold times for nDn input to nLE input.
2000 Mar 09
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet 74AVC16373DGG.PDF ] | |
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